LM3S9B81 Datasheet, PDF (304/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

General-Purpose Input/Outputs (GPIOs)
Table 9-4. GPIO Pad Configuration Examples (continued)
Configuration
GPIO Register Bit Value^a
AFSEL DIR
ODR
DEN
PUR
Digital Output (Timer
1
X
0
1
?
PWM)
Digital Input/Output
1
X
0
1
?
(SSI)
Digital Input/Output
1
X
0
1
?
(UART)
Analog Input
(Comparator)
0
0
0
0
0
Digital Output
(Comparator)
1
X
0
1
?
a. X=Ignored (don’t care bit)
?=Can be either 0 or 1, depending on the configuration
PDR
?
?
?
0
?
DR2R
?
?
?
X
?
DR4R
?
?
?
X
?
DR8R
?
?
?
X
?
SLR
?
?
?
X
?
Table 9-5. GPIO Interrupt Configuration Example
Register
GPIOIS
Desired
Interrupt
Event
Trigger
0=edge
Pin 2 Bit Value^a
7
6
X
X
5
X
4
X
1=level
GPIOIBE
0=single
X
X
X
X
edge
1=both
edges
GPIOIEV 0=Low level,
X
X
X
X
or falling
edge
1=High level,
or rising
edge
GPIOIM
0=masked
0
0
0
0
1=not
masked
a. X=Ignored (don’t care bit)
3
X
X
X
0
2
0
0
1
1
1
X
X
X
0
0
X
X
X
0
9.4 Register Map
Table 9-7 on page 306 lists the GPIO registers. Each GPIO port can be accessed through one of
two bus apertures. The legacy aperture, the Advanced Peripheral Bus (APB), is backwards-compatible
with previous Stellaris^® parts. The other aperture, the Advanced High-Performance Bus (AHB),
offers the same register map but provides better back-to-back access performance than the APB
bus.
Important: The GPIO registers in this chapter are duplicated in each GPIO block; however,
depending on the block, all eight bits may not be connected to a GPIO pad. In those
cases, writing to unconnected bits has no effect, and reading unconnected bits returns
no meaningful data.
304
June 29, 2010
Texas Instruments-Advance Information