LM3S9B81 Datasheet, PDF (600/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Universal Asynchronous Receivers/Transmitters (UARTs)
Register 8: UART Control (UARTCTL), offset 0x030
The UARTCTL register is the control register. All the bits are cleared on reset except for the Transmit
Enable (TXE) and Receive Enable (RXE) bits, which are set.
To enable the UART module, the UARTEN bit must be set. If software requires a configuration change
in the module, the UARTEN bit must be cleared before the configuration changes are written. If the
UART is disabled during a transmit or receive operation, the current transaction is completed prior
to the UART stopping.
Note that bits [15:14,11:10] are only implemented on UART1. These bits are reserved on UART0
and UART2.
Note: The UARTCTL register should not be changed while the UART is enabled or else the results
are unpredictable. The following sequence is recommended for making changes to the
UARTCTL register.
1. Disable the UART.
2. Wait for the end of transmission or reception of the current character.
3. Flush the transmit FIFO by clearing bit 4 (FEN) in the line control register (UARTLCRH).
4. Reprogram the control register.
5. Enable the UART.
UART Control (UARTCTL)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x030
Type R/W, reset 0x0000.0300
31
30
29
28
Type RO
RO
Reset
0
0
15
14
CTSEN RTSEN
Type R/W
R/W
Reset
0
0
RO
RO
0
0
13
12
reserved
RO
RO
0
0
27
RO
0
11
RTS
R/W
0
26
RO
0
10
DTR
R/W
0
25
RO
0
9
RXE
R/W
1
24
23
reserved
RO
RO
0
0
8
7
TXE
LBE
R/W
R/W
1
0
22
21
20
19
18
17
16
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
6
5
4
3
2
1
0
LIN
HSE
EOT SMART SIRLP SIREN UARTEN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Bit/Field
31:16
Name
reserved
Type
RO
Reset
0x0000
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
600
June 29, 2010
Texas Instruments-Advance Information