LM3S9B81 Datasheet, PDF (101/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
6.2.2.4
6.2.2.5
Brown-Out Reset (BOR)
The microcontroller provides a brown-out detection circuit that triggers if the power supply (V_DD)
drops below a brown-out threshold voltage (V_BTH). If a brown-out condition is detected, the system
may generate an interrupt or a system reset. The default condition is to generate an interrupt, so
BOR must be enabled. Brown-out resets are controlled with the Power-On and Brown-Out Reset
Control (PBORCTL) register. The BORIOR bit in the PBORCTL register must be set for a brown-out
condition to trigger a reset; if BORIOR is clear, an interrupt is generated. When a Brown-out condition
occurs during a Flash PROGRAM or ERASE operation, a full system reset is always triggered
without regard to the setting in the PBORCTL register.
The brown-out reset sequence is as follows:
1. When V_DD drops below V_BTH, an internal BOR condition is set.
2. If the BOR condition exists, an internal reset is asserted.
3. The internal reset is released and the microcontroller fetches and loads the initial stack pointer,
the initial program counter, the first instruction designated by the program counter, and begins
execution.
4. The internal BOR condition is reset after 500 µs to prevent another BOR condition from being
set before software has a chance to investigate the original cause.
The result of a brown-out reset is equivalent to that of an assertion of the external RST input, and
the reset is held active until the proper V_DD level is restored. The RESC register can be examined
in the reset interrupt handler to determine if a Brown-Out condition was the cause of the reset, thus
allowing software to determine what actions are required to recover.
The internal Brown-Out Reset timing is shown in Figure 25-6 on page 1089.
Software Reset
Software can reset a specific peripheral or generate a reset to the entire microcontroller.
Peripherals can be individually reset by software via three registers that control reset signals to each
on-chip peripheral (see the SRCRn registers, page 192). If the bit position corresponding to a
peripheral is set and subsequently cleared, the peripheral is reset. The encoding of the reset registers
is consistent with the encoding of the clock gating control for peripherals and on-chip functions (see
“System Control” on page 110).
The entire microcontroller including the core can be reset by software by setting the SYSRESETREQ
bit in the Cortex-M3 Application Interrupt and Reset Control register. The software-initiated system
reset sequence is as follows:
1. A software microcontroller reset is initiated by setting the SYSRESETREQ bit in the ARM
Cortex-M3 Application Interrupt and Reset Control register.
2. An internal reset is asserted.
3. The internal reset is deasserted and the microcontroller loads from memory the initial stack
pointer, the initial program counter, and the first instruction designated by the program counter,
and then begins execution.
The software-initiated system reset timing is shown in Figure 25-7 on page 1089.
June 29, 2010
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Texas Instruments-Advance Information