LM3S9B81 Datasheet, PDF (503/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Figure 13-5. Skewed Sampling
Stellaris® LM3S9B81 Microcontroller
ADC0 S1 S2 S3 S4 S5 S6 S7 S8
ADC1
S1 S2 S3 S4 S5 S6 S7 S8
13.3.2.6
External Voltage Reference
An external reference voltage may be provided to serve as the ADC voltage bias. The VREF bit in
the ADC Control (ADCCTL) register specifies whether to use the internal or external reference.
The ADC conversion value saturates to 0x3FF at the external voltage reference value. The V_REFA
specification defines the useful range for the external voltage reference, see Table 25-25 on page 1096.
Ground is always used as the reference level for the minimum conversion value. Care must be
taken to supply a reference voltage of acceptable quality.
13.3.3
Hardware Sample Averaging Circuit
Higher precision results can be generated using the hardware averaging circuit, however, the
improved results are at the cost of throughput. Up to 64 samples can be accumulated and averaged
to form a single data entry in the sequencer FIFO. Throughput is decreased proportionally to the
number of samples in the averaging calculation. For example, if the averaging circuit is configured
to average 16 samples, the throughput is decreased by a factor of 16.
By default the averaging circuit is off, and all data from the converter passes through to the sequencer
FIFO. The averaging hardware is controlled by the ADC Sample Averaging Control (ADCSAC)
register (see page 537). A single averaging circuit has been implemented, thus all input channels
receive the same amount of averaging whether they are single-ended or differential.
13.3.4
Analog-to-Digital Converter
The Analog-to-Digital Converter (ADC) module uses a Successive Approximation Register (SAR)
architecture to deliver a 10-bit, low-power, high-precision conversion value. The
successive-approximation algorithm uses a current mode D/A converter to achieve lower settling
time, resulting in higher conversion speeds for the A/D converter. In addition, built-in sample-and-hold
circuitry with offset-calibration circuitry improves conversion accuracy. The ADC must be run from
the PLL or a 14- to 18-MHz clock source.
The ADC operates from both the 3.3-V analog and 1.2-V digital power supplies. Integrated shutdown
modes are available to reduce power consumption when ADC conversions are not required. The
analog inputs are connected to the ADC through custom pads and specially balanced input paths
June 29, 2010
503
Texas Instruments-Advance Information