LM3S9B81 Datasheet, PDF (710/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Inter-Integrated Circuit (I²C) Interface
Register 13: I²C Slave Interrupt Mask (I2CSIMR), offset 0x00C
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Slave Interrupt Mask (I2CSIMR)
I2C Slave 0 base: 0x4002.0800
I2C Slave 1 base: 0x4002.1800
Offset 0x00C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
STOPIM STARTIM DATAIM
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:3
2
Name
reserved
STOPIM
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RO
0
Stop Condition Interrupt Mask
Value Description
1 The STOP condition interrupt is sent to the interrupt controller
when the STOPRIS bit in the I2CSRIS register is set.
0 The STOPRIS interrupt is suppressed and not sent to the
interrupt controller.
1
STARTIM
RO
0
Start Condition Interrupt Mask
Value Description
1 The START condition interrupt is sent to the interrupt controller
when the STARTRIS bit in the I2CSRIS register is set.
0 The STARTRIS interrupt is suppressed and not sent to the
interrupt controller.
0
DATAIM
R/W
0
Data Interrupt Mask
Value Description
1 The data received or data requested interrupt is sent to the
interrupt controller when the DATARIS bit in the I2CSRIS register
is set.
0 The DATARIS interrupt is suppressed and not sent to the
interrupt controller.
710
June 29, 2010
Texas Instruments-Advance Information