LM3S9B81 Datasheet, PDF (47/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
1.1.2
1.1.2.1
1.1.2.2
1.1.2.3
■ Dynamically reprioritizable interrupts
■ Exceptional interrupt handling via hardware implementation of required register manipulations
“Interrupts” on page 82 provides an overview of the NVIC controller and the interrupt map. Exceptions
and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual.
On-Chip Memory
The following sections describe the on-chip memory modules.
SRAM (see page 200)
The LM3S9B81 microcontroller provides 96 KB of single-cycle on-chip SRAM. The internal SRAM
of the Stellaris^® devices is located at offset 0x2000.0000 of the device memory map.
Because read-modify-write (RMW) operations are very time consuming, ARM has introduced
bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
Data can be transferred to and from the SRAM using the Micro Direct Memory Access Controller
(µDMA).
Flash Memory (see page 202)
The LM3S9B81 microcontroller provides 256 KB of single-cycle on-chip Flash memory (above 50
MHz, the Flash memory can be accessed in a single cycle as long as the code is linear; branches
incur a one-cycle stall). The Flash memory is organized as a set of 2-KB blocks that can be
individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s.
These blocks are paired into a set of 2-KB blocks that can be individually protected. The blocks can
be marked as read-only or execute-only, providing different levels of code protection. Read-only
blocks cannot be erased or programmed, protecting the contents of those blocks from being modified.
Execute-only blocks cannot be erased or programmed, and can only be read by the controller
instruction fetch mechanism, protecting the contents of those blocks from being read by either the
controller or by a debugger.
ROM (see page 200)
The LM3S9B81 ROM is preprogrammed with the following software and programs:
■ Stellaris^® Peripheral Driver Library
■ Stellaris^® Boot Loader
■ Advanced Encryption Standard (AES) cryptography tables
■ Cyclic Redundancy Check (CRC) error-detection functionality
The Stellaris^® Peripheral Driver Library is a royalty-free software library for controlling on-chip
peripherals with a boot-loader capability. The library performs both peripheral initialization and
control functions, with a choice of polled or interrupt-driven peripheral support. In addition, the library
is designed to take full advantage of the stellar interrupt performance of the ARM® Cortex™-M3
core. No special pragmas or custom assembly code prologue/epilogue functions are required. For
applications that require in-field programmability, the royalty-free Stellaris^® Boot Loader can act as
an application loader and support in-field firmware updates.
June 29, 2010
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Texas Instruments-Advance Information