LM3S9B81 Datasheet, PDF (499/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
Table 13-2. Signals for ADC (108BGA) (continued)
Pin Name
Pin Number Pin Mux / Pin Pin Type Buffer Type^a Description
Assignment
AIN7
B5
PD4
I
Analog Analog-to-digital converter input 7.
AIN8
B4
PE3
I
Analog Analog-to-digital converter input 8.
AIN9
A4
PE2
I
Analog Analog-to-digital converter input 9.
AIN10
A6
PB4
I
Analog Analog-to-digital converter input 10.
AIN11
B7
PB5
I
Analog Analog-to-digital converter input 11.
AIN12
H1
PD3
I
Analog Analog-to-digital converter input 12.
AIN13
H2
PD2
I
Analog Analog-to-digital converter input 13.
AIN14
G2
PD1
I
Analog Analog-to-digital converter input 14.
AIN15
G1
PD0
I
Analog Analog-to-digital converter input 15.
VREFA
A7
PB6
I
Analog This input provides a reference voltage used to
specify the input voltage at which the ADC converts
to a maximum value. In other words, the voltage
that is applied to VREFA is the voltage with which
an AINn signal is converted to 1023. The VREFA
input is limited to the range specified in Table
25-2 on page 1082.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
13.3
Functional Description
The Stellaris^® ADC collects sample data by using a programmable sequence-based approach
instead of the traditional single or double-sampling approaches found on many ADC modules. Each
sample sequence is a fully programmed series of consecutive (back-to-back) samples, allowing the
ADC to collect data from multiple input sources without having to be re-configured or serviced by
the processor. The programming of each sample in the sample sequence includes parameters such
as the input source and mode (differential versus single-ended input), interrupt generation on sample
completion, and the indicator for the last sample in the sequence. In addition, the μDMA can be
used to more efficiently move data from the sample sequencers without CPU intervention.
13.3.1
Sample Sequencers
The sampling control and data capture is handled by the sample sequencers. All of the sequencers
are identical in implementation except for the number of samples that can be captured and the depth
of the FIFO. Table 13-3 on page 499 shows the maximum number of samples that each sequencer
can capture and its corresponding FIFO depth. In this implementation, each FIFO entry is a 32-bit
word, with the lower 10 bits containing the conversion result.
Table 13-3. Samples and FIFO Depth of Sequencers
Sequencer
SS3
SS2
SS1
SS0
Number of Samples
1
4
4
8
Depth of FIFO
1
4
4
8
For a given sample sequence, each sample is defined by two 4-bit nibbles in the ADC Sample
Sequence Input Multiplexer Select (ADCSSMUXn) and ADC Sample Sequence Control
(ADCSSCTLn) registers, where "n" corresponds to the sequence number. The ADCSSMUXn
June 29, 2010
499
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