LM3S9B81 Datasheet, PDF (302/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

General-Purpose Input/Outputs (GPIOs)
9.2.3
9.2.4
■ GPIO Interrupt Both Edges (GPIOIBE) register (see page 311)
■ GPIO Interrupt Event (GPIOIEV) register (see page 312)
Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 313).
When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations:
the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers
(see page 314 and page 315). As the name implies, the GPIOMIS register only shows interrupt
conditions that are allowed to be passed to the interrupt controller. The GPIORIS register indicates
that a GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the
interrupt controller.
In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC.
If PB4 is configured as a non-masked interrupt pin (the appropriate bit of GPIOIM is set), an interrupt
for Port B is generated, and an external trigger signal is sent to the ADC. If the ADC Event
Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC conversion
is initiated. See page 527.
If no other Port B pins are being used to generate interrupts, the ARM Integrated Nested Vectored
Interrupt Controller (NVIC) Interrupt Set Enable (SETNA) register can disable the Port B interrupts,
and the ADC interrupt can be used to read back the converted data. Otherwise, the Port B interrupt
handler must ignore and clear interrupts on PB4 and wait for the ADC interrupt, or the ADC interrupt
must be disabled in the SETNA register and the Port B interrupt handler must poll the ADC registers
until the conversion is completed. See the ARM® Cortex™-M3 Technical Reference Manual for
more information.
Interrupts are cleared by writing a 1 to the appropriate bit of the GPIO Interrupt Clear (GPIOICR)
register (see page 317).
When programming the interrupt control registers (GPIOIS, GPIOIBE, or GPIOIEV), the interrupts
should be masked (GPIOIM cleared). Writing any value to an interrupt control register can generate
a spurious interrupt if the corresponding bits are enabled.
Mode Control
The GPIO pins can be controlled by either software or hardware. Software control is the default for
most signals and corresponds to the GPIO mode, where the GPIODATA register is used to read
or write the corresponding pins. When hardware control is enabled via the GPIO Alternate Function
Select (GPIOAFSEL) register (see page 318), the pin state is controlled by its alternate function
(that is, the peripheral).
Further pin muxing options are provided through the GPIO Port Control (GPIOPCTL) register which
selects one of several peripheral functions for each GPIO. For information on the configuration
options, refer to Table 23-5 on page 1043.
Note: If any pin is to be used as an ADC input, the appropriate bit in the GPIOAMSEL register
must be set to disable the analog isolation circuit.
Commit Control
The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is currently provided for the NMI pin (PB7) and the four
JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select
(GPIOAFSEL) register (see page 318), GPIO Pull Up Select (GPIOPUR) register (see page 324),
GPIO Pull-Down Select (GPIOPDR) register (see page 326), and GPIO Digital Enable (GPIODEN)
register (see page 329) are not committed to storage unless the GPIO Lock (GPIOLOCK) register
302
June 29, 2010
Texas Instruments-Advance Information