LM3S9B81 Datasheet, PDF (815/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
19.4.2
19.5
■ Isolation transformers with integrated RJ45 connector, LEDs and termination resistors
– Pulse J0011D21B/E
– Pulse J3011G21DNL
Software Configuration
To use the Ethernet Controller, it must be enabled by setting the EPHY0 and EMAC0 bits in the
RCGC2 register (see page 183). In addition, the clock to the appropriate GPIO module must be
enabled via the RCGC2 register in the System Control module. See page 183. To find out which
GPIO port to enable, refer to Table 23-4 on page 1036. Configure the PMCn fields in the GPIOPCTL
register to assign the Ethernet signals to the appropriate pins. See page 336 and Table
23-5 on page 1043.
The following steps can then be used to configure the Ethernet Controller for basic operation.
1. Program the MACDIV register to obtain a 2.5 MHz clock (or less) on the internal MII. Assuming
a 20-MHz system clock, the MACDIV value should be 0x03 or greater.
2. Program the MACIA0 and MACIA1 register for address filtering.
3. Program the MACTCTL register for Auto CRC generation, padding, and full-duplex operation
using a value of 0x16.
4. Program the MACRCTL register to flush the receive FIFO and reject frames with bad FCS using
a value of 0x18.
5. Enable both the Transmitter and Receive by setting the LSB in both the MACTCTL and
MACRCTL registers.
6. To transmit a frame, write the frame into the TX FIFO using the Ethernet MAC Data (MACDATA)
register. Then set the NEWTX bit in the Ethernet Mac Transmission Request (MACTR) register
to initiate the transmit process. When the NEWTX bit has been cleared, the TX FIFO is available
for the next transmit frame.
7. To receive a frame, wait for the NPR field in the Ethernet MAC Number of Packets (MACNP)
register to be non-zero. Then begin reading the frame from the RX FIFO by using the MACDATA
register. To ensure that the entire packet is received, either use the DriverLib EthernetPacketGet()
API or compare the number of bytes received to the Length field from the frame to determine
when the packet has been completely read.
Register Map
Table 19-4 on page 816 lists the Ethernet MAC and MII Management registers. The MAC register
addresses given are relative to the Ethernet base address of 0x4004.8000. The MII Management
registers are accessed using the MACMCTL register. Note that the Ethernet controller clocks must
be enabled before the registers can be programmed (see page 183).
The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY
layer. The registers are collectively known as the MII Management registers and are detailed in
Section 22.2.4 of the IEEE 802.3 specification. Table 19-4 on page 816 also lists these MII
Management registers. All addresses given are absolute and are written directly to the REGADR field
of the Ethernet MAC Management Control (MACMCTL) register. The format of registers 0 to 15
are defined by the IEEE specification and are common to all PHY layer implementations. The only
variance allowed is for features that may or may not be supported by a specific PHY implementation.
June 29, 2010
815
Texas Instruments-Advance Information