LM3S9B81 Datasheet, PDF (4/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Table of Contents
5.5.1 Instruction Register (IR) ................................................................................................. 93
5.5.2 Data Registers .............................................................................................................. 95
6
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.3
6.4
6.5
System Control ....................................................................................................... 97
Signal Description ......................................................................................................... 97
Functional Description ................................................................................................... 97
Device Identification ...................................................................................................... 98
Reset Control ................................................................................................................ 98
Non-Maskable Interrupt ............................................................................................... 102
Power Control ............................................................................................................. 103
Clock Control .............................................................................................................. 103
System Control ........................................................................................................... 110
Initialization and Configuration ..................................................................................... 111
Register Map .............................................................................................................. 112
Register Descriptions .................................................................................................. 113
7
7.1
7.2
7.2.1
7.2.2
7.2.3
7.3
7.3.1
7.3.2
7.3.3
7.4
7.5
7.6
Internal Memory ................................................................................................... 199
Block Diagram ............................................................................................................ 199
Functional Description ................................................................................................. 199
SRAM ........................................................................................................................ 200
ROM .......................................................................................................................... 200
Flash Memory ............................................................................................................. 202
Flash Memory Initialization and Configuration ............................................................... 203
Flash Memory Programming ........................................................................................ 203
32-Word Flash Memory Write Buffer ............................................................................. 205
Nonvolatile Register Programming ............................................................................... 205
Register Map .............................................................................................................. 206
Flash Memory Register Descriptions (Flash Control Offset) ............................................ 207
Memory Register Descriptions (System Control Offset) .................................................. 218
8
Micro Direct Memory Access (μDMA) ................................................................ 236
8.1 Block Diagram ............................................................................................................ 237
8.2 Functional Description ................................................................................................. 237
8.2.1 Channel Assignments .................................................................................................. 238
8.2.2 Priority ........................................................................................................................ 239
8.2.3 Arbitration Size ............................................................................................................ 239
8.2.4 Request Types ............................................................................................................ 239
8.2.5 Channel Configuration ................................................................................................. 240
8.2.6 Transfer Modes ........................................................................................................... 242
8.2.7 Transfer Size and Increment ........................................................................................ 250
8.2.8 Peripheral Interface ..................................................................................................... 250
8.2.9 Software Request ........................................................................................................ 250
8.2.10 Interrupts and Errors .................................................................................................... 251
8.3 Initialization and Configuration ..................................................................................... 251
8.3.1 Module Initialization ..................................................................................................... 251
8.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 251
8.3.3 Configuring a Peripheral for Simple Transmit ................................................................ 253
8.3.4 Configuring a Peripheral for Ping-Pong Receive ............................................................ 254
8.3.5 Configuring Channel Assignments ................................................................................ 257
8.4 Register Map .............................................................................................................. 257
8.5 μDMA Channel Control Structure ................................................................................. 258
4
June 29, 2010
Texas Instruments-Advance Information