LM3S9B81 Datasheet, PDF (679/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
Table 16-2. Signals for I2C (108BGA) (continued)
Pin Name
I2C0SDA
I2C1SCL
I2C1SDA
Pin Number Pin Mux / Pin
Assignment
E11
PB3 (1)
F3
PJ0 (11)
K1
PG0 (3)
L3
PA0 (8)
L6
PA6 (1)
K2
PG1 (3)
M3
PA1 (8)
M6
PA7 (1)
B6
PJ1 (11)
Pin Type
I/O
I/O
I/O
Buffer Type^a Description
OD
I²C module 0 data.
OD
I²C module 1 clock.
OD
I²C module 1 data.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
16.3
Functional Description
Each I²C module is comprised of both master and slave functions which are implemented as separate
peripherals. For proper operation, the SDA and SCL pins must be connected to bi-directional
open-drain pads. A typical I²C bus configuration is shown in Figure 16-2.
See “Inter-Integrated Circuit (I²C) Interface” on page 1098 for I²C timing diagrams.
Figure 16-2. I²C Bus Configuration
SCL
SDA
RPUP RPUP
I2C Bus
I2CSCL I2CSDA
Stellaris®
SCL
SDA
3rd Party Device
with I2C Interface
SCL
SDA
3rd Party Device
with I2C Interface
16.3.1
I²C Bus Functional Overview
The I²C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris^®
microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock
line. The bus is considered idle when both lines are High.
Every transaction on the I²C bus is nine bits long, consisting of eight data bits and a single
acknowledge bit. The number of bytes per transfer (defined as the time between a valid START
and STOP condition, described in “START and STOP Conditions” on page 679) is unrestricted, but
each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When
a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force the
transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL.
16.3.1.1
START and STOP Conditions
The protocol of the I²C bus defines two states to begin and end a transaction: START and STOP.
A High-to-Low transition on the SDA line while the SCL is High is defined as a START condition,
and a Low-to-High transition on the SDA line while SCL is High is defined as a STOP condition.
The bus is considered busy after a START condition and free after a STOP condition. See Figure
16-3.
June 29, 2010
679
Texas Instruments-Advance Information