LM3S9B81 Datasheet, PDF (76/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

ARM Cortex-M3 Processor Core
2.2.7.1
2.2.8
2.2.8.1
Interrupts
The ARM® Cortex™-M3 Technical Reference Manual describes the maximum number of interrupts
and interrupt priorities. The LM3S9B81 microcontroller supports 47 interrupts with eight priority
levels.
In addition to the peripheral interrupts, the system also provides for a non-maskable interrupt (NMI).
The NMI is generally used in safety critical applications where the immediate execution of an interrupt
handler is required. The NMI signal is available as an external signal so that it may be generated
by external circuitry. The NMI is also used internally as part of the main oscillator verification circuitry.
More information on the non-maskable interrupt is located in “Non-Maskable Interrupt” on page 102.
System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine
■ A high-speed alarm timer using the system clock
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter used to measure time to completion and time used
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
Functional Description
The timer consists of three registers:
■ SysTick Control and Status Register - a control and status counter to configure its clock, enable
the counter, enable the SysTick interrupt, and determine counter status
■ SysTick Reload Value Register - the reload value for the counter, used to provide the counter's
wrap value
■ SysTick Current Value Register - the current value of the counter
A fourth register, the SysTick Calibration Value Register, is not implemented in the Stellaris^® devices.
When enabled, the timer counts down on each clock from the reload value to zero, reloads (wraps)
to the value in the SysTick Reload Value register on the next clock edge, then decrements on
subsequent clocks. Clearing the SysTick Reload Value register disables the counter on the next
wrap. When the counter reaches zero, the COUNTFLAG status bit is set. The COUNTFLAG bit
clears on reads.
Writing to the SysTick Current Value register clears the register and the COUNTFLAG status bit.
The write does not trigger the SysTick exception logic. On a read, the current value is the value of
the register at the time the register is accessed.
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June 29, 2010
Texas Instruments-Advance Information