LM3S9B81 Datasheet, PDF (71/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
Table 2-2. 32-Bit Cortex-M3 Instruction Set Summary (continued)
Operation
Assembler
Bitwise AND register value with shifted register value
AND{S}.W <Rd>, <Rn>, Rm>{, <shift>}
Arithmetic shift right by number in register
ASR{S}.W <Rd>, <Rn>, <Rm>
Conditional branch
B{cond}.W <label>
Clear bit field
BFC.W <Rd>, #<lsb>, #<width>
Insert bit field from one register value into another
BFI.W <Rd>, <Rn>, #<lsb>, #<width>
Bitwise AND register value with complement of immediate 12-bit value
BIC{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
Bitwise AND register value with complement of shifted register value
BIC{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Branch with link
BL <label>
Branch with link (immediate)
BL<c> <label>
Unconditional branch
B.W <label>
Clear exclusive clears the local record of the executing processor that an CLREX <c>
address has had a request for an exclusive access.
Return number of leading zeros in register value
CLZ.W <Rd>, <Rn>
Compare register value with two’s complement of immediate 12-bit value CMN.W <Rn>, #<modify_constant(immed_12)>
Compare register value with two’s complement of shifted register value
CMN.W <Rn>, <Rm>{, <shift>}
Compare register value with immediate 12-bit value
CMP.W <Rn>, #<modify_constant(immed_12)>
Compare register value with shifted register value
CMP.W <Rn>, <Rm>{, <shift>}
Data memory barrier
DMB <c>
Data synchronization barrier
DSB <c>
Exclusive OR register value with immediate 12-bit value
EOR{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
Exclusive OR register value with shifted register value
EOR{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Instruction synchronization barrier
ISB <c>
Load multiple memory registers, increment after or decrement before
LDM{IA|DB}.W <Rn>{!}, <registers>
Memory word from base register address + immediate 12-bit offset
LDR.W <Rxf>, [<Rn>, #<offset_12>]
Memory word to PC from register address + immediate 12-bit offset
LDR.W PC, [<Rn>, #<offset_12>]
Memory word to PC from base register address immediate 8-bit offset,
postindexed
LDR.W PC, [Rn], #<+/-<offset_8>
Memory word from base register address immediate 8-bit offset, postindexed LDR.W <Rxf>, [<Rn>], #+/–<offset_8>
Memory word from base register address immediate 8-bit offset, preindexed LDR.W <Rxf>, [<Rn>, #<+/–<offset_8>]!
LDRT.W <Rxf>, [<Rn>, #<offset_8>]
Memory word to PC from base register address immediate 8-bit offset,
preindexed
LDR.W PC, [<Rn>, #+/–<offset_8>]!
Memory word from register address shifted left by 0, 1, 2, or 3 places
LDR.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Memory word to PC from register address shifted left by 0, 1, 2, or 3 places LDR.W PC, [<Rn>, <Rm>{, LSL #<shift>}]
Memory word from PC address immediate 12-bit offset
LDR.W <Rxf>, [PC, #+/–<offset_12>]
Memory word to PC from PC address immediate 12-bit offset
LDR.W PC, [PC, #+/–<offset_12>]
Memory byte [7:0] from base register address + immediate 12-bit offset
LDRB.W <Rxf>, [<Rn>, #<offset_12>]
Memory byte [7:0] from base register address immediate 8-bit offset,
postindexed
LDRB.W <Rxf>. [<Rn>], #+/-<offset_8>
Memory byte [7:0] from register address shifted left by 0, 1, 2, or 3 places LDRB.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Memory byte [7:0] from base register address immediate 8-bit offset,
preindexed
LDRB.W <Rxf>, [<Rn>, #<+/–<offset_8>]!
Memory byte from PC address immediate 12-bit offset
LDRB.W <Rxf>, [PC, #+/–<offset_12>]
Memory doubleword from register address 8-bit offset 4, preindexed
LDRD.W <Rxf>, <Rxf2>, [<Rn>, #+/–<offset_8> * 4]{!}
June 29, 2010
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