LM3S9B81 Datasheet, PDF (421/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
Register 32: EPI Error Interrupt Status and Clear (EPIEISC), offset 0x21C
This register is used to clear a pending error interrupt. If any of these bits are set, the ERRRIS bit
in the EPIRIS register is set, and an EPI controller error is sent to the interrupt controller if the ERIM
bit in the EPIIM register is set. Clearing any defined bit has no effect; setting a bit clears the error
source and the raw error returns to 0. Note that writing to this register and reading back immediately
(pipelined by the processor) returns the old register contents. One cycle is needed between write
and read.
EPI Error Interrupt Status and Clear (EPIEISC)
Base 0x400D.0000
Offset 0x21C
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
WTFULL RSTALL TOUT
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO R/W1C R/W1C R/W1C
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:3
2
1
Name
reserved
WTFULL
RSTALL
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W1C
0
Write FIFO Full Error
Value Description
1 The WFERR bit is enabled and a write is stalled due to the WFIFO
being full.
0 The WFERR bit is not enabled or no writes are stalled.
Writing a 1 to this bit clears it and the WFERR bit in the EPIFIFOLVL
register.
R/W1C
0
Read Stalled Error
Value Description
1 The RSERR bit is enabled and a pending read is stalled due to
writes in the WFIFO.
0 The RSERR bit is not enabled pr no pending reads are stalled.
Writing a 1 to this bit clears it and the RSERR bit in the EPIFIFOLVL
register.
June 29, 2010
421
Texas Instruments-Advance Information