LM3S9B81 Datasheet, PDF (431/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
for at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is 1/4 of the system frequency.
In Edge-Count mode, the timer is configured as a 24-bit down-counter with the MSB stored in the
GPTM Timer n Prescale (GPTMTnPR) register and the remaining 16 bits in the GPTMTnILR
register. In this mode, the timer is capable of capturing three types of events: rising edge, falling
edge, or both. To place the timer in Edge-Count mode, the TnCMR bit of the GPTMTnMR register
must be cleared. The type of edge that the timer counts is determined by the TnEVENT fields of the
GPTMCTL register. During initialization, the GPTM Timer n Match (GPTMTnMATCHR) register is
configured so that the difference between the value in the GPTMTnILR register and the
GPTMTnMATCHR register equals the number of edge events that must be counted.
When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled
for event capture. Each input event on the CCP pin decrements the counter by 1 until the event count
matches GPTMTnMATCHR. When the counts match, the GPTM asserts the CnMRIS bit in the
GPTMRIS register (and the CnMMIS bit, if the interrupt is not masked).
In addition to generating interrupts, a μDMA trigger can be generated. The μDMA trigger is enabled
by configuring and enabling the appropriate μDMA channel. See “Channel Configuration” on page 240.
The counter is then reloaded using the value in GPTMTnILR, and stopped because the GPTM
automatically clears the TnEN bit in the GPTMCTL register. Once the event count has been reached,
all further events are ignored until TnEN is re-enabled by software.
Figure 11-2 on page 431 shows how Input Edge-Count mode works. In this case, the timer start
value is set to GPTMnILR =0x000A and the match value is set to GPTMnMATCHR =0x0006 so
that four edge events are counted. The counter is configured to detect both edges of the input signal.
Note that the last two edges are not counted since the timer automatically clears the TnEN bit after
the current count matches the value in the GPTMnMR register.
Figure 11-2. 16-Bit Input Edge-Count Mode Example
Count
Timer stops,
flags
asserted
Timer reload
on next cycle Ignored
Ignored
0x000A
0x0009
0x0008
0x0007
0x0006
Input Signal
June 29, 2010
431
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