LM3S9B81 Datasheet, PDF (111/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
Peripherals are clocked that are enabled in the SCGCn register when auto-clock gating is enabled
(see the RCC register) or the RCGCn register when the auto-clock gating is disabled. The system
clock has the same source and frequency as that during Run mode.
■ Deep-Sleep Mode. In Deep-Sleep mode, the clock frequency of the active peripherals may
change (depending on the Run mode clock configuration) in addition to the processor clock being
stopped. An interrupt returns the microcontroller to Run mode from one of the sleep modes; the
sleep modes are entered on request from the code. Deep-Sleep mode is entered by first writing
the Deep Sleep Enable bit in the ARM Cortex-M3 NVIC system control register and then executing
a WFI instruction. Any properly configured interrupt event in the system brings the processor
back into Run mode. See the system control NVIC section of the ARM® Cortex™-M3 Technical
Reference Manual for more details.
The Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are
clocked that are enabled in the DCGCn register when auto-clock gating is enabled (see the RCC
register) or the RCGCn register when auto-clock gating is disabled. The system clock source is
specified in the DSLPCLKCFG register. When the DSLPCLKCFG register is used, the internal
oscillator source is powered up, if necessary, and other clocks are powered down. If the PLL is
running at the time of the WFI instruction, hardware powers the PLL down and overrides the
SYSDIV field of the active RCC/RCC2 register, to be determined by the DSDIVORIDE setting in
the DSLPCLKCFG register, up to /16 or /64 respectively. When the Deep-Sleep exit event
occurs, hardware brings the system clock back to the source and frequency it had at the onset
of Deep-Sleep mode before enabling the clocks that had been stopped during the Deep-Sleep
duration. If the PIOSC is used as the PLL reference clock source, it may continue to provide the
clock during Deep-Sleep. See page 136.
Caution – If the Cortex-M3 Debug Access Port (DAP) has been enabled, and the device wakes from a
low power sleep or deep-sleep mode, the core may start executing code before all clocks to peripherals
have been restored to their run mode configuration. The DAP is usually enabled by software tools
accessing the JTAG or SWD interface when debugging or flash programming. If this condition occurs,
a Hard Fault is triggered when software accesses a peripheral with an invalid clock.
A software delay loop can be used at the beginning of the interrupt routine that is used to wake up a
system from a WFI (Wait For Interrupt) instruction. This stalls the execution of any code that accesses
a peripheral register that might cause a fault. This loop can be removed for production software as the
DAP is most likely not enabled during normal execution.
Because the DAP is disabled by default (power on reset), the user can also power cycle the device. The
DAP is not enabled unless it is enabled through the JTAG or SWD interface.
6.3 Initialization and Configuration
The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register
is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps
required to successfully change the PLL-based system clock are:
1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS
bit in the RCC register, thereby configuring the microcontroller to run off a “raw” clock source
and allowing for the new PLL configuration to be validated before switching the system clock
to the PLL.
2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in
RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the
appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output.
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