LM3S9B81 Datasheet, PDF (240/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Micro Direct Memory Access (μDMA)
8.2.4.1
8.2.4.2
8.2.5
transfer, then the burst request takes precedence. See Table 8-2, which shows how each peripheral
supports the two request types.
Table 8-2. Request Type Support
Peripheral
USB TX
USB RX
Ethernet TX
Ethernet RX
UART TX
UART RX
SSI TX
SSI RX
ADC
General-Purpose Timer
I²S TX
I²S RX
EPI WFIFO
EPI NBRFIFO
Single Request Signal
None
None
TX FIFO empty
RX packet received
TX FIFO Not Full
RX FIFO Not Empty
TX FIFO Not Full
RX FIFO Not Empty
None
None
None
None
None
None
Burst Request Signal
FIFO TXRDY
FIFO RXRDY
None
None
TX FIFO Level (configurable)
RX FIFO Level (configurable)
TX FIFO Level (fixed at 4)
RX FIFO Level (fixed at 4)
Sequencer IE bit
Raw interrupt pulse
FIFO service request
FIFO service request
WFIFO Level (configurable)
NBRFIFO Level (configurable)
Single Request
When a single request is detected, and not a burst request, the μDMA controller transfers one item
and then stops to wait for another request.
Burst Request
When a burst request is detected, the μDMA controller transfers the number of items that is the
lesser of the arbitration size or the number of items remaining in the transfer. Therefore, the arbitration
size should be the same as the number of data items that the peripheral can accommodate when
making a burst request. For example, the UART generates a burst request based on the FIFO trigger
level. In this case, the arbitration size should be set to the amount of data that the FIFO can transfer
when the trigger level is reached. A burst transfer runs to completion once it is started, and cannot
be interrupted, even by a higher priority channel. Burst transfers complete in a shorter time than the
same number of non-burst transfers.
It may be desirable to use only burst transfers and not allow single transfers. For example, perhaps
the nature of the data is such that it only makes sense when transferred together as a single unit
rather than one piece at a time. The single request can be disabled by using the DMA Channel
Useburst Set (DMAUSEBURSTSET) register. By setting the bit for a channel in this register, the
μDMA controller only responds to burst requests for that channel.
Channel Configuration
The μDMA controller uses an area of system memory to store a set of channel control structures
in a table. The control table may have one or two entries for each μDMA channel. Each entry in the
table structure contains source and destination pointers, transfer size, and transfer mode. The
control table can be located anywhere in system memory, but it must be contiguous and aligned on
a 1024-byte boundary.
Table 8-3 on page 241 shows the layout in memory of the channel control table. Each channel may
have one or two control structures in the control table: a primary control structure and an optional
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June 29, 2010
Texas Instruments-Advance Information