LM3S9B81 Datasheet, PDF (380/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

External Peripheral Interface (EPI)
Register 1: EPI Configuration (EPICFG), offset 0x000
Important: The MODE field determines which configuration register is accessed for offsets 0x010
and 0x014. Any write to the EPICFG register resets the register contents at offsets
0x010 and 0x014.
The configuration register is used to enable the block, select a mode, and select the basic pin use
(based on the mode). Note that attempting to program an undefined MODE field clears the BLKEN
bit and disables the EPI controller.
EPI Configuration (EPICFG)
Base 0x400D.0000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
BLKEN
MODE
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:5
4
Name
reserved
BLKEN
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
0
Block Enable
Value Description
1 The EPI controller is enabled.
0 The EPI controller is disabled.
380
June 29, 2010
Texas Instruments-Advance Information