LM3S9B81 Datasheet, PDF (59/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
1.1.5.5
1.1.5.6
The LM3S9B81 microcontroller includes eight Capture Compare PWM pins (CCP) that can be
programmed to operate in the following modes:
■ Capture: The GP Timer is incremented/decremented by programmed events on the CCP input.
The GP Timer captures and stores the current timer value when a programmed event occurs.
■ Compare: The GP Timer is incremented/decremented by programmed events on the CCP input.
The GP Timer compares the current value with a stored value and generates an interrupt when
a match occurs.
■ PWM: The GP Timer is incremented/decremented by the system clock. A PWM signal is generated
based on a match between the counter value and a value stored in a match register and is output
on the CCP pin.
Watchdog Timers (see page 471)
A watchdog timer is used to regain control when a system has failed due to a software error or to
the failure of an external device to respond in the expected way. The Stellaris^® Watchdog Timer
can generate an interrupt or a reset when a time-out value is reached. In addition, the Watchdog
Timer is ARM FiRM-compliant and can be configured to generate an interrupt to the controller on
its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer
has been configured, the lock register can be written to prevent the timer configuration from being
inadvertently altered.
The LM3S9B81 microcontroller has two Watchdog Timer modules: Watchdog Timer 0 uses the
system clock for its timer clock; Watchdog Timer 1 uses the PIOSC as its timer clock. The Stellaris^®
Watchdog Timer module has the following features:
■ 32-bit down counter with a programmable load register
■ Separate watchdog clock with an enable
■ Programmable interrupt generation logic with interrupt masking
■ Lock register protection from runaway software
■ Reset generation logic with an enable/disable
■ User-enabled stalling when the microcontroller asserts the CPU Halt flag during debug
Programmable GPIOs (see page 294)
General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The Stellaris^®
GPIO module is comprised of nine physical GPIO blocks, each corresponding to an individual GPIO
port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP for Real-Time
Microcontrollers specification) and supports 0-65 programmable input/output pins. The number of
GPIOs available depends on the peripherals being used (see “Signal Tables” on page 1017 for the
signals available to each GPIO pin).
■ Up to 65 GPIOs, depending on configuration
■ Highly flexible pin muxing allows use as GPIO or one of several peripheral functions
■ 5-V-tolerant input/outputs
■ Fast toggle capable of a change every two clock cycles
June 29, 2010
59
Texas Instruments-Advance Information