LM3S9B81 Datasheet, PDF (1066/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Signal Tables
Table 23-8. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin Pin Type Buffer Type^a Description
Assignment
USB0DP
C12
fixed
I/O
Analog Bidirectional differential data pin (D+ per USB
specification).
USB0EPEN
K1
PG0 (7)
O
M1
PC5 (6)
L6
PA6 (8)
A11
PB2 (8)
D10
PH3 (4)
TTL
Optionally used in Host mode to control an external
power source to supply power to the USB bus.
USB0ID
E12
PB0
I
Analog This signal senses the state of the USB ID signal.
The USB PHY enables an integrated pull-up, and
an external element (USB connector) indicates the
initial state of the USB controller (pulled down is
the A side of the cable and pulled up is the B side).
USB0PFLT
L2
PC7 (6)
I
M2
PC6 (7)
M6
PA7 (8)
E11
PB3 (8)
B11
PE0 (9)
B10
PH4 (4)
B6
PJ1 (9)
TTL
Optionally used in Host mode by an external power
source to indicate an error state by that power
source.
USB0RBIAS
B12
fixed
O
Analog 9.1-kΩ resistor (1% precision) used internally for
USB analog circuitry.
USB0VBUS
D12
PB1
I/O
Analog This signal is used during the session request
protocol. This signal allows the USB PHY to both
sense the voltage level of VBUS, and pull up VBUS
momentarily during VBUS pulsing.
VDD
K7
fixed
-
Power Positive supply for I/O and some logic.
G12
K8
K9
H10
G10
E10
G11
VDDA
C7
fixed
-
Power The positive supply (3.3 V) for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from VDD to minimize the electrical noise
contained on VDD from affecting the analog
functions. VDDA pins must be connected to 3.3 V,
regardless of system implementation.
VDDC
D3
fixed
C3
-
Power Positive supply for most of the logic function,
including the processor core and most peripherals.
VREFA
A7
PB6
I
Analog This input provides a reference voltage used to
specify the input voltage at which the ADC converts
to a maximum value. In other words, the voltage
that is applied to VREFA is the voltage with which
an AINn signal is converted to 1023. The VREFA
input is limited to the range specified in Table
25-2 on page 1082.
XTALNPHY
J1
fixed
O
Analog Ethernet PHY XTALN 25-MHz oscillator crystal
output.
XTALPPHY
J2
fixed
I
Analog Ethernet PHY XTALP 25-MHz oscillator crystal
input.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
1066
Texas Instruments-Advance Information
June 29, 2010