LM3S9B81 Datasheet, PDF (362/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

External Peripheral Interface (EPI)
If one of the Dual-Chip-Select modes is selected (CSCFG=0x2 or 0x3 in the EPIHBnCFG2 register),
both chip selects can share the peripheral or the memory space, or one chip select can use the
peripheral space and the other can use the memory space. In the EPIADDRMAP register, if the
EPADR field is not 0x0 and the ERADR field is 0x0, then the address specified by EPADR is used for
both chip selects, with CS0n being asserted when the MSB of the address range is 0 and CS1n
being asserted when the MSB of the address range is 1. If the ERADR field is not 0x0 and the EPADR
field is 0x0, then the address specified by ERADR is used for both chip selects, with the MSB
performing the same delineation. If both the EPADR and the ERADR are not 0x0, then CS0n is asserted
for the address range defined by EPADR and CS1n is asserted for the address range defined by
ERADR. If the CSBAUD bit in the EPIHBnCFG2 register is set, the 2 chip selects can use different
clock frequencies. If the CSBAUD bit is clear, both chip selects use the clock frequency, wait states,
and strobe polarity defined for CS0n.
When BSEL=1 in the EPIHB16CFG register, byte select signals are provided, so byte-sized data
can be read and written at any address, however these signals reduce the available address width
by 2 pins. The byte select signals are active low. BSEL0n corresponds to the LSB of the halfword,
and BSEL1n corresponds to the MSB of the halfword.
When BSEL=0, byte reads and writes at odd addresses only act on the even byte, and byte writes
at even addresses write invalid values into the odd byte. As a result, accesses should be made as
half-words (16-bits) or words (32-bits). In C/C++, programmers should use only short int and long
int for accesses. Also, because data accesses in HB16 mode with no byte selects are on 2-byte
boundaries, the available address space is doubled. For example, 28 bits of address accesses 512
MB in this mode. Table 10-4 on page 362 shows the capabilities of the HB8 and HB16 modes as
well as the available address bits with the possible combinations of these bits.
Although the EPI0S31 signal can be configured for the EPI clock signal in Host-Bus mode, it is not
required and should be configured as a GPIO to reduce EMI in the system.
Table 10-4. Capabilities of Host Bus 8 and Host Bus 16 Modes
Host Bus Type
MODE
HB8
0x0
HB8
0x0
HB8
0x0
HB8
0x1
HB8
0x1
HB8
0x1
HB8
0x3
HB8
0x3
HB16
0x0
HB16
0x0
HB16
0x0
HB16
0x0
HB16
0x0
HB16
0x0
HB16
0x1
HB16
0x1
HB16
0x1
CSCFG
0x0, 0x1
0x2
0x3
0x0, 0x1
0x2
0x3
0x1
0x3
0x0, 0x1
0x0, 0x1
0x2
0x2
0x3
0x3
0x0, 0x1
0x0, 0x1
0x2
Max # of
External
Devices
1
2
2
1
2
2
1
2
1
1
2
2
2
2
1
1
2
BSEL
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
1
0
1
0
1
0
1
0
Byte Access
Always
Always
Always
Always
Always
Always
Always
Always
No
Yes
No
Yes
No
Yes
No
Yes
No
Available Address
28 bits
27 bits
26 bits
20 bits
19 bits
18 bits
none
none
28 bits^a
26 bits
27 bits^a
25 bits
26 bits^a
24 bits
12 bits^a
10 bits
11 bits^a
362
June 29, 2010
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