LM3S9B81 Datasheet, PDF (77/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
2.2.8.2
2.2.8.3
If the core is in debug state (halted), the counter does not decrement. The timer is clocked with
respect to a reference clock, which can be either the core clock or an external clock source.
SysTick Control and Status Register
Use the SysTick Control and Status Register to enable the SysTick features. The reset is
0x0000.0000.
Bit/Field
31:17
Name
reserved
Type
RO
16 COUNTFLAG R/W
15:3
reserved
RO
2 CLKSOURCE R/W
Reset Description
0x000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 Count Flag
When set, this bit indicates that the timer has counted to 0 since the last time
this register was read.
This bit is cleared by a read of the register.
If read by the debugger using the DAP, this bit is cleared only if the
MasterType bit in the AHB-AP Control Register is clear. Otherwise, the
COUNTFLAG bit is not changed by the debugger read.
0x000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0 Clock Source
Value Description
0 External reference clock. (Not implemented for Stellaris^®
microcontrollers.)
1 Core clock
Because an external reference clock is not supported, this bit must be set
in order for SysTick to operate.
1
TICKINT
R/W
0 Tick Interrupt
When set, this bit causes an interrupt to be generated to the NVIC when
SysTick counts to 0.
When clear, interrupt generation is disabled. Software can use the
COUNTFLAG to determine if the counter has ever reached 0.
0
ENABLE
R/W
0 Enable
When set, this bit enables SysTick to operate in a multi-shot way. That is,
the counter loads the Reload value and begins counting down. On reaching
0, the COUNTFLAG bit is set and an interrupt is generated if enabled by
TICKINT. The counter then loads the Reload value again and begins counting.
When this bit is clear, the counter is disabled.
SysTick Reload Value Register
The SysTick Reload Value Register specifies the start value to load into the SysTick Current Value
Register when the counter reaches 0. The start value can be between 1 and 0x00FF.FFFF. A start
value of 0 is possible but has no effect because the SysTick interrupt and COUNTFLAG are activated
when counting from 1 to 0.
SysTick can be configured as a multi-shot timer, repeated over and over, firing every N+1 clock
pulses, where N is any value from 1 to 0x00FF.FFFF. For example, if a tick interrupt is required
every 100 clock pulses, 99 must be written into the RELOAD field.
June 29, 2010
77
Texas Instruments-Advance Information