LM3S9B81 Datasheet, PDF (45/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
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In addition, the LM3S9B81 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S9B81 microcontroller is code-compatible
to all members of the extensive Stellaris^® family; providing flexibility to fit our customers' precise
needs.
Texas Instruments offers a complete solution to get to market quickly, with evaluation and
development boards, white papers and application notes, an easy-to-use peripheral driver library,
and a strong support, sales, and distributor network. See “Ordering and Contact
Information” on page 1147 for ordering information for Stellaris^® family devices.
Functional Overview
The following sections provide an overview of the features of the LM3S9B81 microcontroller. The
page number in parentheses indicates where that feature is discussed in detail. Ordering and support
information can be found in “Ordering and Contact Information” on page 1147.
ARM Cortex™-M3
The following sections provide an overview of the ARM Cortex™-M3 processor core and instruction
set, the integrated System Timer (SysTick) and the Nested Vectored Interrupt Controller.
Processor Core (see page 66)
All members of the Stellaris^® product family, including the LM3S9B81 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for
a high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
■ 32-bit ARM® Cortex™-M3 architecture optimized for small-footprint embedded applications
■ Outstanding processing performance combined with fast interrupt handling
■ Thumb-2 mixed 16-/32-bit instruction set, delivers the high performance expected of a 32-bit
ARM core in a compact memory size usually associated with 8- and 16-bit devices; typically in
the range of a few kilobytes of memory for microcontroller-class applications
– Single-cycle multiply instruction and hardware divide
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
– Unaligned data access, enabling data to be efficiently packed into memory
■ Fast code execution permits slower processor clock or increases sleep mode time
■ Harvard architecture characterized by separate buses for instruction and data
■ Efficient processor core, system and memories
■ Hardware division and fast multiplier
■ Deterministic, high-performance interrupt handling for time-critical applications
June 29, 2010
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