LM3S9B81 Datasheet, PDF (860/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Ethernet Controller
Register 28: Ethernet PHY Management Register 30 – Interrupt Mask (MR30),
address 0x1E
This register enables interrupts to be generated by the various sources of PHY layer interrupts.
Ethernet PHY Management Register 30 – Interrupt Mask (MR30)
Base 0x4004.8000
Address 0x1E
Type R/W, reset 0x0000
15
14
13
12
11
10
9
8
7
6
5
reserved
EONIM ANCOMPIM RFLTIM
Type RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
4
3
2
LDIM LPACKIM PDFIM
R/W
R/W
R/W
0
0
0
1
PRXIM
R/W
0
0
reserved
R/W
0
Bit/Field
15:8
7
Name
reserved
EONIM
Type
RO
R/W
Reset
0x00
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ENERGYON Interrupt Enabled
Value Description
1 An interrupt is sent to the interrupt controller when the EONIS
bit in the MR29 register is set.
0 The EONIS interrupt is suppressed and not sent to the interrupt
controller.
6
ANCOMPIM
R/W
0
Auto-Negotiation Complete Interrupt Enabled
Value Description
1 An interrupt is sent to the interrupt controller when the
ANCOMPIS bit in the MR29 register is set.
0 The ANCOMPIS interrupt is suppressed and not sent to the
interrupt controller.
5
RFLTIM
R/W
0
Remote Fault Interrupt Enabled
Value Description
1 An interrupt is sent to the interrupt controller when the RFLTIS
bit in the MR29 register is set.
0 The RFLTIS interrupt is suppressed and not sent to the interrupt
controller.
4
LDIM
R/W
0
Link Down Interrupt Enabled
Value Description
1 An interrupt is sent to the interrupt controller when the LDIS bit
in the MR29 register is set.
0 The LDIS interrupt is suppressed and not sent to the interrupt
controller.
860
June 29, 2010
Texas Instruments-Advance Information