LM3S9B81 Datasheet, PDF (1108/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
15
14
13
12
11
10
9
8
7
6
5
Micro Direct Memory Access (μDMA)
μDMA Channel Control Structure (Offset from Channel Control Table Base)
Base n/a
DMASRCENDP, type R/W, offset 0x000, reset -
ADDR
ADDR
DMADSTENDP, type R/W, offset 0x004, reset -
ADDR
ADDR
DMACHCTL, type R/W, offset 0x008, reset -
DSTINC
ARBSIZE
DSTSIZE
SRCINC
SRCSIZE
XFERSIZE
Micro Direct Memory Access (μDMA)
μDMA Registers (Offset from μDMA Base Address)
Base 0x400F.F000
DMASTAT, type RO, offset 0x000, reset 0x001F.0000
DMACFG, type WO, offset 0x004, reset -
STATE
DMACTLBASE, type R/W, offset 0x008, reset 0x0000.0000
ADDR
DMAALTBASE, type RO, offset 0x00C, reset 0x0000.0200
DMAWAITSTAT, type RO, offset 0x010, reset 0x0000.0000
DMASWREQ, type WO, offset 0x014, reset -
DMAUSEBURSTSET, type R/W, offset 0x018, reset 0x0000.0000
DMAUSEBURSTCLR, type WO, offset 0x01C, reset -
DMAREQMASKSET, type R/W, offset 0x020, reset 0x0000.0000
DMAREQMASKCLR, type WO, offset 0x024, reset -
DMAENASET, type R/W, offset 0x028, reset 0x0000.0000
DMAENACLR, type WO, offset 0x02C, reset -
ADDR
ADDR
ADDR
WAITREQ[n]
WAITREQ[n]
SWREQ[n]
SWREQ[n]
SET[n]
SET[n]
CLR[n]
CLR[n]
SET[n]
SET[n]
CLR[n]
CLR[n]
SET[n]
SET[n]
CLR[n]
CLR[n]
20
19
18
17
16
4
3
2
1
0
NXTUSEBURST
ARBSIZE
XFERMODE
DMACHANS
MASTEN
MASTEN
1108
Texas Instruments-Advance Information
June 29, 2010