LM3S9B81 Datasheet, PDF (368/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

External Peripheral Interface (EPI)
bits in the EPIHBnCFG2 register. Each wait state adds 2 EPI clock cycles to the duration of the
WRn or RDn strobe.
Figure 10-5 on page 368 shows a basic Host-Bus read cycle. Figure 10-6 on page 368 shows a basic
Host-Bus write cycle. Both of these figures show address and data signals in the non-multiplexed
mode (MODE field ix 0x1 in the EPIHBnCFG register).
Figure 10-5. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 1, RDHIGH = 1
ALE
(EPI0S30)
CSn
(EPI0S30)
WRn
(EPI0S29)
RDn/OEn
(EPI0S28)
BSEL0n/
BSEL1n^a
Address
Data
a _{BSEL0n and BSEL1n are available in Host-Bus 16 mode only.}
Data
Figure 10-6. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 1, RDHIGH = 1
ALE
(EPI0S30)
CSn
(EPI0S30)
WRn
(EPI0S29)
RDn/OEn
(EPI0S28)
BSEL0n/
BSEL1n^a
Address
Data
a _{BSEL0n and BSEL1n are available in Host-Bus 16 mode only.}
Data
Figure 10-7 on page 369 shows a write cycle with the address and data signals multiplexed (MODE
field is 0x0 in the EPIHBnCFG register). A read cycle would look similar, with the RDn strobe being
asserted along with CSn and data being latched on the rising edge of RDn.
368
June 29, 2010
Texas Instruments-Advance Information