LM3S9B81 Datasheet, PDF (428/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

General-Purpose Timers
11.3.2
32-Bit Timer Operating Modes
This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) and their
configurations.
The GPTM is placed into 32-bit mode by writing a 0x0 (One-Shot/Periodic 32-bit timer mode) or a
0x1 (RTC mode) to the GPTMCFG bit field in the GPTM Configuration (GPTMCFG) register. In both
configurations, certain GPTM registers are concatenated to form pseudo 32-bit registers. These
registers include:
■ GPTM Timer A Interval Load (GPTMTAILR) register [15:0], see page 458
■ GPTM Timer B Interval Load (GPTMTBILR) register [15:0], see page 459
■ GPTM Timer A (GPTMTAR) register [15:0], see page 466
■ GPTM Timer B (GPTMTBR) register [15:0], see page 467
■ GPTM Timer A Value (GPTMTAV) register [15:0], see page 469
■ GPTM Timer B Value (GPTMTBV) register [15:0], see page 470
In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access
to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is:
GPTMTBILR[15:0]:GPTMTAILR[15:0]
Likewise, a 32-bit read access to GPTMTAR returns the value:
GPTMTBR[15:0]:GPTMTAR[15:0]
A 32-bit read access to GPTMTAV returns the value:
GPTMTBV[15:0]:GPTMTAV[15:0]
11.3.2.1
32-Bit One-Shot/Periodic Timer Mode
In 32-bit one-shot and periodic timer modes, the concatenated versions of the Timer A and Timer
B registers are configured as a 32-bit up or down counter. The selection of one-shot or periodic
mode is determined by the value written to the TAMR field of the GPTM Timer A Mode (GPTMTAMR)
register (see page 441); there is no need to write to the GPTM Timer B Mode (GPTMTBMR) register.
The timer is configured to count up or down using the TACDIR bit in the GPTMTAMR register.
When software sets the TAEN bit in the GPTM Control (GPTMCTL) register (see page 445), the
timer begins counting up from 0x0000.0000 or down from its preloaded value. Alternatively, if the
TAWOT bit is set in the GPTMTAMR register, once the TAEN bit is set, the timer waits for a trigger
to begin counting (see “Wait-for-Trigger Mode” on page 434).
When the timer is counting down and it reaches the time-out event (0x0000.0000), the timer reloads
its start value from the concatenated GPTMTAILR on the next cycle. When the timer is counting
up and it reaches the time-out event (the value in the concatenated GPTMTAILR), the timer starts
counting again from 0x0000.0000 on the next cycle. If configured to be a one-shot timer, the timer
stops counting and clears the TAEN bit in the GPTMCTL register. If configured as a periodic timer,
it continues counting. In periodic, snap-shot mode (TASNAPS bit in the GPTMTAMR register is set),
the actual free-running value of the timer at the time-out event is loaded into the GPTMTAR register.
In this manner, software can determine the time elapsed from the interrupt assertion to the ISR
entry.
428
June 29, 2010
Texas Instruments-Advance Information