LM3S9B81 Datasheet, PDF (360/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

External Peripheral Interface (EPI)
halfword of data is received, signaling the end of the cycle. At least one clock period of inactivity
separates any two SDRAM cycles.
Figure 10-3. SDRAM Normal Read Cycle
CLK
(EPI0S31)
CKE
(EPI0S30)
CSn
(EPI0S29)
WEn
(EPI0S28)
RASn
(EPI0S19)
CASn
(EPI0S18)
DQMH, DQML
(EPI0S [17:16])
AD [15:0]
(EPI0S [15:0])
Row
Activate
NOP
AD [15:0] driven out
NOP
Column
Read
NOP
AD [15:0] driven out
Data 0
Data 1
AD [15:0] driven in
10.4.1.6
Write Cycle
Figure 10-4 on page 361 shows a write cycle of n halfwords; n can be any number greater than or
equal to 1. The cycle begins with the Activate command and the row address on the EPI0S[15:0]
signals. With the programmed CAS latency of 2, the Write command with the column address on
the EPI0S[15:0] signals follows after 2 clock cycles. When writing to SDRAMs, the Write command
is presented with the first halfword of data. Because the address lines and the data lines are
multiplexed, the column address is modified to be (programmed address -1). During the Write
command, the DQMH and DQML signals are high, so no data is written to the SDRAM. On the next
clock, the DQMH and DQML signals are asserted, and the data associated with the programmed
address is written. The Burst Terminate command occurs during the clock cycle following the write
of the last halfword of data. The WEn, DQMH, DQML, and CSn signals are deasserted after the
last halfword of data is received, signaling the end of the access. At least one clock period of inactivity
separates any two SDRAM cycles.
360
June 29, 2010
Texas Instruments-Advance Information