LM3S9B81 Datasheet, PDF (73/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
Table 2-2. 32-Bit Cortex-M3 Instruction Set Summary (continued)
Operation
Assembler
Logical OR NOT register value with immediate 12-bit value
ORN{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
Logical OR NOT register value with shifted register value
ORN[S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Logical OR register value with immediate 12-bit value
ORR{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
Logical OR register value with shifted register value
ORR{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Reverse bit order
RBIT.W <Rd>, <Rm>
Reverse bytes in word
REV.W <Rd>, <Rm>
Reverse bytes in each halfword
REV16.W <Rd>, <Rn>
Reverse bytes in bottom halfword and sign-extend
REVSH.W <Rd>, <Rn>
Rotate right by number in register
ROR{S}.W <Rd>, <Rn>, <Rm>
Rotate right with extend
RRX{S}.W <Rd>, <Rm>
Subtract a register value from an immediate 12-bit value
RSB{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
Subtract a register value from a shifted register value
RSB{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Subtract immediate 12-bit value and C bit from register value
SBC{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
Subtract shifted register value and C bit from register value
SBC{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Copy selected bits to register and sign-extend
SBFX.W <Rd>, <Rn>, #<lsb>, #<width>
Signed divide
SDIV<c> <Rd>,<Rn>,<Rm>
Send event
SEV<c>
Multiply signed words and add signed-extended value to 2-register value SMLAL.W <RdLo>, <RdHi>, <Rn>, <Rm>
Multiply two signed register values
SMULL.W <RdLo>, <RdHi>, <Rn>, <Rm>
Signed saturate
SSAT.W <c> <Rd>, #<imm>, <Rn>{, <shift>}
Multiple register words to consecutive memory locations
STM{IA|DB}.W <Rn>{!}, <registers>
Register word to register address + immediate 12-bit offset
STR.W <Rxf>, [<Rn>, #<offset_12>]
Register word to register address immediate 8-bit offset, postindexed
STR.W <Rxf>, [<Rn>], #+/–<offset_8>
Register word to register address shifted by 0, 1, 2, or 3 places
STR.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Register word to register address immediate 8-bit offset, preindexed Store, STR.W <Rxf>, [<Rn>, #+/-<offset_8>]{!}
preindexed
STRT.W <Rxf>, [<Rn>, #<offset_8>]
Register byte [7:0] to register address immediate 8-bit offset, preindexed STRB{T}.W <Rxf>, [<Rn>, #+/–<offset_8>]{!}
Register byte [7:0] to register address + immediate 12-bit offset
STRB.W <Rxf>, [<Rn>, #<offset_12>]
Register byte [7:0] to register address immediate 8-bit offset, postindexed STRB.W <Rxf>, [<Rn>], #+/–<offset_8>
Register byte [7:0] to register address shifted by 0, 1, 2, or 3 places
STRB.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Store doubleword, preindexed
STRD.W <Rxf>, <Rxf2>, [<Rn>, #+/–<offset_8> * 4]{!}
Store doubleword, postindexed
STRD.W <Rxf>, <Rxf2>, [<Rn>, #+/–<offset_8> * 4]
Store register exclusive calculates an address from a base register value and STREX <c> <Rd>,<Rt>,[<Rn>{,#<imm>}]
an immediate offset, and stores a word from a register to memory if the
executing processor has exclusive access to the memory addressed.
Store register exclusive byte derives an address from a base register value, STREXB <c> <Rd>,<Rt>,[<Rn>]
and stores a byte from a register to memory if the executing processor has
exclusive access to the memory addressed
Store register exclusive halfword derives an address from a base register
value, and stores a halfword from a register to memory if the executing
processor has exclusive access to the memory addressed.
STREXH <c> <Rd>,<Rt>,[<Rn>]
Register halfword [15:0] to register address + immediate 12-bit offset
STRH.W <Rxf>, [<Rn>, #<offset_12>]
Register halfword [15:0] to register address shifted by 0, 1, 2, or 3 places STRH.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Register halfword [15:0] to register address immediate 8-bit offset, preindexed STRH{T}.W <Rxf>, [<Rn>, #+/–<offset_8>]{!}
June 29, 2010
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