LM3S9B81 Datasheet, PDF (11/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
Figure 10-21. EPI Clock Operation, CLKGATE=1, WR2CYC=0 ................................................. 377
Figure 10-22. EPI Clock Operation, CLKGATE=1, WR2CYC=1 ................................................. 378
Figure 11-1. GPTM Module Block Diagram ............................................................................ 424
Figure 11-2. 16-Bit Input Edge-Count Mode Example .............................................................. 431
Figure 11-3. 16-Bit Input Edge-Time Mode Example ............................................................... 433
Figure 11-4. 16-Bit PWM Mode Example ................................................................................ 434
Figure 11-5. Timer Daisy Chain ............................................................................................. 434
Figure 12-1. WDT Module Block Diagram .............................................................................. 472
Figure 13-1. Implementation of Two ADC Blocks .................................................................... 497
Figure 13-2. ADC Module Block Diagram ............................................................................... 497
Figure 13-3. ADC Sample Phases ......................................................................................... 502
Figure 13-4. Doubling the ADC Sample Rate .......................................................................... 502
Figure 13-5. Skewed Sampling .............................................................................................. 503
Figure 13-6. Internal Voltage Conversion Result ..................................................................... 504
Figure 13-7. External Voltage Conversion Result .................................................................... 505
Figure 13-8. Differential Sampling Range, V_{IN_ODD} = 1.5 V ...................................................... 506
Figure 13-9. Differential Sampling Range, V_{IN_ODD} = 0.75 V .................................................... 507
Figure 13-10. Differential Sampling Range, V_{IN_ODD} = 2.25 V .................................................... 507
Figure 13-11. Internal Temperature Sensor Characteristic ......................................................... 508
Figure 13-12. Low-Band Operation (CIC=0x0 and/or CTC=0x0) ................................................ 511
Figure 13-13. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ................................................. 512
Figure 13-14. High-Band Operation (CIC=0x3 and/or CTC=0x3) ................................................ 513
Figure 14-1. UART Module Block Diagram ............................................................................. 574
Figure 14-2. UART Character Frame ..................................................................................... 577
Figure 14-3. IrDA Data Modulation ......................................................................................... 579
Figure 14-4. LIN Message ..................................................................................................... 581
Figure 14-5. LIN Synchronization Field ................................................................................... 582
Figure 15-1. SSI Module Block Diagram ................................................................................. 636
Figure 15-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 640
Figure 15-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 640
Figure 15-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 641
Figure 15-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 641
Figure 15-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 642
Figure 15-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 643
Figure 15-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 643
Figure 15-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 644
Figure 15-10. MICROWIRE Frame Format (Single Frame) ........................................................ 645
Figure 15-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 646
Figure 15-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 646
Figure 16-1. I²C Block Diagram ............................................................................................. 678
Figure 16-2. I²C Bus Configuration ........................................................................................ 679
Figure 16-3. START and STOP Conditions ............................................................................. 680
Figure 16-4. Complete Data Transfer with a 7-Bit Address ....................................................... 680
Figure 16-5. R/S Bit in First Byte ............................................................................................ 680
Figure 16-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 681
Figure 16-7. Master Single TRANSMIT .................................................................................. 684
Figure 16-8. Master Single RECEIVE ..................................................................................... 685
Figure 16-9. Master TRANSMIT with Repeated START ........................................................... 686
June 29, 2010
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