LM3S9B81 Datasheet, PDF (448/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

General-Purpose Timers
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018
This register allows software to enable/disable GPTM controller-level interrupts. Setting a bit enables
the corresponding interrupt, while clearing a bit disables it.
GPTM Interrupt Mask (GPTMIMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x018
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
15
Type RO
Reset
0
14
13
reserved
RO
RO
0
0
12
11
10
9
8
7
6
5
TBMIM CBEIM CBMIM TBTOIM
reserved
RO
R/W
R/W
R/W
R/W
RO
RO
RO
0
0
0
0
0
0
0
0
20
19
18
17
16
RO
RO
RO
RO
RO
0
0
0
0
0
4
3
2
1
0
TAMIM RTCIM CAEIM CAMIM TATOIM
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Bit/Field
31:12
11
Name
reserved
TBMIM
Type
RO
R/W
Reset Description
0x0000.0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
GPTM Timer B Mode Match Interrupt Mask
The TBMIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
10
CBEIM
R/W
0
GPTM Capture B Event Interrupt Mask
The CBEIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
9
CBMIM
R/W
0
GPTM Capture B Match Interrupt Mask
The CBMIM values are defined as follows:
Value Description
0 Interrupt is disabled.
1 Interrupt is enabled.
448
June 29, 2010
Texas Instruments-Advance Information