LM3S9B81 Datasheet, PDF (105/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
■ System clock derived from PLL or other clock source
■ Enabling/disabling of oscillators and PLL
■ Clock divisors
■ Crystal input selection
Figure 6-5 shows the logic for the main clock tree. The peripheral blocks are driven by the system
clock signal and can be individually enabled/disabled. The ADC clock signal is automatically divided
down to 16 MHz for proper ADC operation.
Note: When the ADC module is in operation, the system clock must be at least 16 MHz.
June 29, 2010
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Texas Instruments-Advance Information