LM3S9B81 Datasheet, PDF (367/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
register, EPI0S30 functions as ALE, EPI0S27 functions as CS1n, and EPI0S26 functions as
CS0n. The CSn is best used for Host-Bus unmuxed mode which EPI address and data pins
are separate. The CSn indicates when the address and data phases of a read or write access
are occurring.
2. Address and data are separate with 8 or 16 bits of data and up to 20 bits of address (1 MB).
This scheme is used by more modern 8051 devices, as well as some PIC and ATmega parts.
This mode is generally used with real SRAMs, many EEPROMs, and many NOR Flash memory
devices. Note that there is no hardware command write support for Flash memory devices; this
mode should only be used for Flash memory devices programmed at manufacturing time. If a
Flash memory device must be written and does not support a direct programming model, the
command mechanism must be performed in software. The CSn configuration should be used
in this mode. The CSn signal indicates when the address and data phases of a read or write
access is occurring. The CSn configuration is controlled by configuring the CSCFG field to be
0x1 in the EPIHBnCFG2 register.
3. Continuous read mode where address and data are separate. This sub-mode is used for real
SRAMs which can be read more quickly by only changing the address (and not using RDn/OEn
strobing). In this sub-mode, reads are performed by keeping the read mode selected (output
enable is asserted) and then changing the address pins. The data pins are changed by the
SRAM after the address pins change. For example, to read data from address 0x100 and then
0x101, the EPI controller asserts the output-enable signal and then configures the address pins
to 0x100; the EPI controller then captures what is on the data pins and increments A0 to 1 (so
the address is now 0x101); the EPI controller then captures what is on the data pins. Note that
this mode consumes higher power because the SRAM must continuously drive the data pins.
This mode is not practical in HB16 mode for normal SRAMs because there are generally not
enough address bits available.
4. FIFO mode uses 8 or 16 bits of data, removes ALE and address pins and optionally adds external
XFIFO FULL/EMPTY flag inputs. This scheme is used by many devices, such as radios,
communication devices (including USB2 devices), and some FPGA configurations (FIFO through
block RAM). This sub-mode provides the data side of the normal Host-Bus interface, but is
paced by the FIFO control signals. It is important to consider that the XFIFO FULL/EMPTY
control signals may stall the interface and could have an impact on blocking read latency from
the processor or μDMA.
The WORD bit in the EPIHBnCFG2 register can be set to use memory more efficiently. By default,
the EPI controller uses data bits [7:0] for Host-Bus 8 accesses or bits [15:0] for Host-Bus 16 accesses.
When the WORD bit is set, the EPI controller can automatically route bytes of data onto the correct
byte lanes such that data can be stored in bits [31:8] (HB8) or [31:16] (HB16). In addition, for the
three modes above (1, 2, 4) that the Host-Bus 16 mode supports, byte select signals can be optionally
implemented by setting the BSEL bit in the EPIHB16CFG register.
See “External Peripheral Interface (EPI)” on page 1090 for timing details for the Host-Bus mode.
10.4.2.4
Bus Operation
Bus operation is the same in Host-Bus 8 and Host-Bus 16 modes and is asynchronous. Timing
diagrams show both ALE and CSn operation, but only one signal or the other is used in all modes
except for ALE with dual chip selects mode (CSCFG field is 0x3 in the EPIHBnCFG2 register).
Address and data on write cycles are held after the CSn signal is deasserted. The optional HB16
byte select signals have the same timing as the address signals. If wait states are required in the
bus access, they can be inserted during the data phase of the access using the WRWS and RDWS
June 29, 2010
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