LM3S9B81 Datasheet, PDF (696/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Inter-Integrated Circuit (I²C) Interface
Write-Only Control Register
I2C Master Control/Status (I2CMCS)
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
Offset 0x004
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
ACK STOP START RUN
Type WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:4
3
Name
reserved
ACK
Type
Reset Description
WO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
WO
0
Data Acknowledge Enable
Value Description
0 The received data byte is not acknowledged automatically by
the master.
1 The received data byte is acknowledged automatically by the
master. See field decoding in Table 16-5 on page 697.
2
STOP
WO
0
Generate STOP
Value Description
0 The controller does not generate the STOP condition.
1 The controller generates the STOP condition. See field decoding
in Table 16-5 on page 697.
1
START
WO
0
Generate START
Value Description
0 The controller does not generate the START condition.
1 The controller generates the START or repeated START
condition. See field decoding in Table 16-5 on page 697.
0
RUN
WO
0
I²C Master Enable
Value Description
0 The master is disabled.
1 The master is enabled to transmit or receive data. See field
decoding in Table 16-5 on page 697.
696
June 29, 2010
Texas Instruments-Advance Information