LM3S9B81 Datasheet, PDF (67/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
2.1
For more information on the ARM Cortex-M3 processor core, see the ARM® Cortex™-M3 Technical
Reference Manual. For information on SWJ-DP, see the ARM® CoreSight Technical Reference
Manual.
Block Diagram
Figure 2-1. CPU Block Diagram
Nested
Vectored
Interrupt
Controller
Interrupts
Sleep
Debug
CM3 Core
Instructions Data
Memory
Protection
Unit
ARM
Cortex-M3
Serial
Wire
Output
Trace
Trace ^Port
Port ^(SWO)
Interface
Unit
Serial Wire JTAG
Debug Port
Flash
Patch and
Breakpoint
Private Peripheral
Bus
(internal)
Debug
Access Port
Data Instrumentation
Watchpoint Trace Macrocell
and Trace
ROM
Table
Bus
Matrix
Adv. Peripheral
Bus
I-code bus
D-code bus
System bus
2.2
2.2.1
Functional Description
Important: The ARM® Cortex™-M3 Technical Reference Manual describes all the features of an
ARM Cortex-M3 in detail. However, these features differ based on the implementation.
This section describes the Stellaris^® implementation.
Texas Instruments implements the ARM Cortex-M3 core as shown in Figure 2-1 on page 67. The
Cortex-M3 uses the entire 16-bit Thumb instruction set and the base Thumb-2 32-bit instruction set.
In addition, as noted in the ARM® Cortex™-M3 Technical Reference Manual, several Cortex-M3
components are flexible in their implementation: SW/JTAG-DP, ETM, TPIU, the ROM table, the
MPU, and the Nested Vectored Interrupt Controller (NVIC). Each of these is addressed in the
sections that follow.
Programming Model
This section provides a brief overview of the programming model for the Cortex-M3 core. More
detailed information can be found in the ARM® Cortex™-M3 Technical Reference Manual.
■ Privileged access and user access - Code can execute as privileged or unprivileged. Unprivileged
execution limits or excludes access to some resources. Privileged execution has access to all
resources. Handler mode is always privileged. Thread mode can be privileged or unprivileged.
June 29, 2010
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