LM3S9B81 Datasheet, PDF (377/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
iRDY Signal Operation
The ready input (iRDY) from the external device is enabled by the RDYEN bit in the EPIGPCFG
register. iRDY is input on EPI0S27 and may only be used with a free-running clock (CLKGATE is
clear). iRDY is sampled on the falling edge of the EPI clock and gates transactions, no matter what
state they are in. Figure 10-20 on page 377 shows the iRDY signal being recognized as deasserted
on the falling edge of T1. The FRAME, RD, Address, Data signals behave as they would during a
normal transaction in T1. T2 is the frozen state, and signals are held in this state until iRDY is
recognized as asserted again. At the falling edge of T2, when iRDY is asserted again, the cycle
continues and completes in T3.
Figure 10-20. iRDY Signal Operation, FRM50=0, FRMCNT=0, and RD2CYC=1
T0
T1
T2
T3
Clock (EPI0S31)
Frame
(EPI0S30)
RD (EPI0S29)
iRDY (EPI0S27)
Address
Data
EPI Clock Operation
If the CLKGATE bit in the EPIGPCFG register is clear, the EPI clock always toggles when
General-purpose mode is enabled. If CLKGATE is set, the clock is output only when a transaction
is occurring, otherwise the clock is held high. If the WR2CYC bit is clear, the EPI clock begins toggling
1 cycle before the WR strobe goes high. If the WR2CYC bit is set, the EPI clock begins toggling when
the WR strobe goes high. The clock stops toggling after the first rising edge after the WR strobe is
deasserted. The RD strobe operates in the same manner as the WR strobe when the WR2CYC bit
is set, as the RD2CYC bit must always be set. See Figure 10-21 on page 377 and Figure
10-22 on page 378.
Figure 10-21. EPI Clock Operation, CLKGATE=1, WR2CYC=0
Clock
(EPI0S31)
WR
(EPI0S28)
Address
Data
June 29, 2010
377
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