LM3S9B81 Datasheet, PDF (26/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Table of Contents
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ................................................................. 799
CAN Transmission Request 1 (CANTXRQ1), offset 0x100 ................................................ 800
CAN Transmission Request 2 (CANTXRQ2), offset 0x104 ................................................ 800
CAN New Data 1 (CANNWDA1), offset 0x120 ................................................................. 801
CAN New Data 2 (CANNWDA2), offset 0x124 ................................................................. 801
CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ..................................... 802
CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ..................................... 802
CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ....................................................... 803
CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ....................................................... 803
Ethernet Controller ...................................................................................................................... 804
Register 1: Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 ....... 818
Register 2: Ethernet MAC Interrupt Mask (MACIM), offset 0x004 ....................................................... 821
Register 3: Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................ 823
Register 4: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ............................................... 825
Register 5: Ethernet MAC Data (MACDATA), offset 0x010 ................................................................. 827
Register 6: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 ............................................. 829
Register 7: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 ............................................. 830
Register 8: Ethernet MAC Threshold (MACTHR), offset 0x01C .......................................................... 831
Register 9: Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................ 833
Register 10: Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... 835
Register 11: Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. 836
Register 12: Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 .............................. 837
Register 13: Ethernet MAC Number of Packets (MACNP), offset 0x034 ............................................... 838
Register 14: Ethernet MAC Transmission Request (MACTR), offset 0x038 ........................................... 839
Register 15: Ethernet MAC LED Encoding (MACLED), offset 0x040 .................................................... 840
Register 16: Ethernet PHY MDIX (MDIX), offset 0x044 ....................................................................... 842
Register 17: Ethernet PHY Management Register 0 – Control (MR0), address 0x00 ............................. 843
Register 18: Ethernet PHY Management Register 1 – Status (MR1), address 0x01 .............................. 845
Register 19: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 ................. 847
Register 20: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 ................. 848
Register 21: Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address
0x04 ............................................................................................................................. 849
Register 22: Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability
(MR5), address 0x05 ..................................................................................................... 851
Register 23: Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address
0x06 ............................................................................................................................. 853
Register 24: Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 ............. 854
Register 25: Ethernet PHY Management Register 17 – Mode Control/Status (MR17), address 0x11 ...... 855
Register 26: Ethernet PHY Management Register 27 – Special Control/Status (MR27), address
0x1B ............................................................................................................................. 857
Register 27: Ethernet PHY Management Register 29 – Interrupt Status (MR29), address 0x1D ............. 858
Register 28: Ethernet PHY Management Register 30 – Interrupt Mask (MR30), address 0x1E ............... 860
Register 29: Ethernet PHY Management Register 31 – PHY Special Control/Status (MR31), address
0x1F ............................................................................................................................. 862
Universal Serial Bus (USB) Controller ....................................................................................... 863
Register 1: USB Device Functional Address (USBFADDR), offset 0x000 ............................................ 891
Register 2: USB Power (USBPOWER), offset 0x001 ......................................................................... 892
Register 3: USB Transmit Interrupt Status (USBTXIS), offset 0x002 ................................................... 895
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June 29, 2010
Texas Instruments-Advance Information