LM3S9B81 Datasheet, PDF (14/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Table of Contents
List of Tables
Table 1.
Table 2.
Table 2-1.
Table 2-2.
Table 3-1.
Table 4-1.
Table 4-2.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 6-1.
Table 6-2.
Table 6-3.
Table 6-4.
Table 6-5.
Table 6-6.
Table 6-7.
Table 6-8.
Table 6-9.
Table 7-1.
Table 7-2.
Table 7-3.
Table 8-1.
Table 8-2.
Table 8-3.
Table 8-4.
Table 8-5.
Table 8-6.
Table 8-7.
Table 8-8.
Table 8-9.
Table 8-10.
Table 8-11.
Table 8-12.
Table 8-13.
Table 9-1.
Table 9-2.
Table 9-3.
Table 9-4.
Table 9-5.
Table 9-6.
Table 9-7.
Table 9-8.
Table 9-9.
Revision History .................................................................................................. 35
Documentation Conventions ................................................................................ 41
16-Bit Cortex-M3 Instruction Set Summary ............................................................ 68
32-Bit Cortex-M3 Instruction Set Summary ............................................................ 70
Memory Map ....................................................................................................... 79
Exception Types .................................................................................................. 82
Interrupts ............................................................................................................ 83
Signals for JTAG_SWD_SWO (100LQFP) ............................................................. 86
Signals for JTAG_SWD_SWO (108BGA) .............................................................. 87
JTAG Port Pins State after Power-On Reset or RST assertion ................................ 88
JTAG Instruction Register Commands ................................................................... 93
Signals for System Control & Clocks (100LQFP) ................................................... 97
Signals for System Control & Clocks (108BGA) ..................................................... 97
Reset Sources .................................................................................................... 98
Clock Source Options ........................................................................................ 104
Possible System Clock Frequencies Using the SYSDIV Field ............................... 107
Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 107
Examples of Possible System Clock Frequencies with DIV400=1 ......................... 108
System Control Register Map ............................................................................. 112
RCC2 Fields that Override RCC fields ................................................................. 132
Flash Memory Protection Policy Combinations .................................................... 203
User-Programmable Flash Memory Resident Registers ....................................... 206
Flash Register Map ............................................................................................ 206
μDMA Channel Assignments .............................................................................. 238
Request Type Support ....................................................................................... 240
Control Structure Memory Map ........................................................................... 241
Channel Control Structure .................................................................................. 241
μDMA Read Example: 8-Bit Peripheral ................................................................ 250
μDMA Interrupt Assignments .............................................................................. 251
Channel Control Structure Offsets for Channel 30 ................................................ 252
Channel Control Word Configuration for Memory Transfer Example ...................... 252
Channel Control Structure Offsets for Channel 7 .................................................. 253
Channel Control Word Configuration for Peripheral Transmit Example .................. 254
Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 255
Channel Control Word Configuration for Peripheral Ping-Pong Receive
Example ............................................................................................................ 256
μDMA Register Map .......................................................................................... 257
GPIO Pins With Non-Zero Reset Values .............................................................. 295
GPIO Pins and Alternate Functions (100LQFP) ................................................... 295
GPIO Pins and Alternate Functions (108BGA) ..................................................... 297
GPIO Pad Configuration Examples ..................................................................... 303
GPIO Interrupt Configuration Example ................................................................ 304
GPIO Pins With Non-Zero Reset Values .............................................................. 305
GPIO Register Map ........................................................................................... 306
GPIO Pins With Non-Zero Reset Values .............................................................. 318
GPIO Pins With Non-Zero Reset Values .............................................................. 324
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June 29, 2010
Texas Instruments-Advance Information