LM3S9B81 Datasheet, PDF (18/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Table of Contents
List of Registers
System Control .............................................................................................................................. 97
Register 1: Device Identification 0 (DID0), offset 0x000 ..................................................................... 114
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................ 116
Register 3: Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 117
Register 4: Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 119
Register 5: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 121
Register 6: Reset Cause (RESC), offset 0x05C ................................................................................ 123
Register 7: Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 125
Register 8: XTAL to PLL Translation (PLLCFG), offset 0x064 ............................................................. 129
Register 9: GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C ................................... 130
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 132
Register 11: Main Oscillator Control (MOSCCTL), offset 0x07C ........................................................... 135
Register 12: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 136
Register 13: Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 ................................... 138
Register 14: I²S MCLK Configuration (I2SMCLKCFG), offset 0x170 ..................................................... 139
Register 15: Device Identification 1 (DID1), offset 0x004 ..................................................................... 141
Register 16: Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 143
Register 17: Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 144
Register 18: Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 147
Register 19: Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 149
Register 20: Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 152
Register 21: Device Capabilities 5 (DC5), offset 0x020 ........................................................................ 154
Register 22: Device Capabilities 6 (DC6), offset 0x024 ........................................................................ 155
Register 23: Device Capabilities 7 (DC7), offset 0x028 ........................................................................ 156
Register 24: Device Capabilities 8 ADC Channels (DC8), offset 0x02C ................................................ 160
Register 25: Device Capabilities 9 ADC Digital Comparators (DC9), offset 0x190 ................................. 163
Register 26: Non-Volatile Memory Information (NVMSTAT), offset 0x1A0 ............................................. 165
Register 27: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 166
Register 28: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 169
Register 29: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 172
Register 30: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 174
Register 31: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 177
Register 32: Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 180
Register 33: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 183
Register 34: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 186
Register 35: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 189
Register 36: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 192
Register 37: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 194
Register 38: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 197
Internal Memory ........................................................................................................................... 199
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 208
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 209
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 210
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 212
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 213
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June 29, 2010
Texas Instruments-Advance Information