LM3S9B81 Datasheet, PDF (429/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
In addition to reloading the count value, the GPTM generates interrupts and triggers when it reaches
the time-out event. The GPTM sets the TATORIS bit in the GPTM Raw Interrupt Status (GPTMRIS)
register (see page 450), and holds it until it is cleared by writing the GPTM Interrupt Clear (GPTMICR)
register (see page 456). If the time-out interrupt is enabled in the GPTM Interrupt Mask (GPTIMR)
register (see page 448), the GPTM also sets the TATOMIS bit in the GPTM Masked Interrupt Status
(GPTMMIS) register (see page 453). By setting the TAMIE bit in the GPTMTAMR register, an interrupt
can also be generated when the Timer A value equals the value loaded into the GPTM Timer A
Match (GPTMTAMATCH) register. This interrupt has the same status, masking, and clearing
functions as the time-out interrupt. The ADC trigger is enabled by setting the TAOTE bit in GPTMCTL.
The μDMA trigger is enabled by configuring and enabling the appropriate μDMA channel. See
“Channel Configuration” on page 240.
If software updates the GPTMTAILR register while the counter is counting down, the counter loads
the new value on the next clock cycle and continues counting down from the new value. If software
updates the GPTM Timer A Value (GPTMTAV) register while the counter is counting up or down,
the counter loads the new value on the next clock cycle and continues counting from the new value.
If the TASTALL bit in the GPTMCTL register is set, the timer freezes counting while the processor
is halted by the debugger. The timer resumes counting when the processor resumes execution.
11.3.2.2
32-Bit Real-Time Clock Timer Mode
In Real-Time Clock (RTC) mode, the concatenated versions of the Timer A and Timer B registers
are configured as a 32-bit up-counter. When RTC mode is selected for the first time after reset, the
counter is loaded with a value of 0x0000.0001. All subsequent load values must be written to the
GPTM Timer A Interval Load (GPTMTAILR) register (see page 458).
The input clock on an even CCP input is required to be 32.768 KHz in RTC mode. The clock signal
is then divided down to a 1-Hz rate and is passed along to the input of the 32-bit counter.
When software writes the TAEN bit in the GPTMCTL register, the counter starts counting up from
its preloaded value of 0x0000.0001. When the current count value matches the preloaded value in
the GPTMTAMATCHR register, the GPTM asserts the RTCRIS bit in GPTMRIS and continues
counting until either a hardware reset, or it is disabled by software (clearing the TAEN bit). When
the timer value reaches 0xFFFF.FFFF, the timer rolls over and continues counting up from 0x0. If
the RTC interrupt is enabled in GPTIMR, the GPTM also sets the RTCMIS bit in GPTMISR and
generates a controller interrupt. The status flags are cleared by writing the RTCCINT bit in GPTMICR.
In addition to generating interrupts, a μDMA trigger can be generated. The μDMA trigger is enabled
by configuring and enabling the appropriate μDMA channel. See “Channel Configuration” on page 240.
If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if
the RTCEN bit is set in GPTMCTL.
11.3.3
16-Bit Timer Operating Modes
The GPTM is placed into global 16-bit mode by writing a value of 0x4 to the GPTM Configuration
(GPTMCFG) register (see page 440). This section describes each of the GPTM 16-bit modes of
operation. Timer A and Timer B have identical modes, so a single description is given using an n
to reference both.
11.3.3.1
16-Bit One-Shot/Periodic Timer Mode
In 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit up or down-counter
with an optional 8-bit prescaler that effectively extends the counting range of the timer to 24 bits.
The selection of one-shot or periodic mode is determined by the value written to the TnMR field of
the GPTMTnMR register. The optional prescaler is loaded into the GPTM Timer n Prescale
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