LM3S9B81 Datasheet, PDF (430/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

General-Purpose Timers
(GPTMTnPR) register. The timer is configured to count up or down using the TnCDIR bit in the
GPTMTnMR register.
When software sets the TnEN bit in the GPTMCTL register, the timer begins counting up from
0x0000.0000 or down from its preloaded value. Alternatively, if the TnWOT bit is set in the GPTMTnMR
register, once the TnEN bit is set, the timer waits for a trigger to begin counting (see “Wait-for-Trigger
Mode” on page 434).
When the timer is counting down and it reaches the time-out event (0x0000), the timer reloads its
start value from the concatenated GPTMTnILR and GPTMTnPR on the next cycle. When the timer
is counting up and it reaches the time-out event (the value in the GPTMTnILR), the timer starts
counting again from 0x0000 on the next cycle. If configured to be a one-shot timer, the timer stops
counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, it
continues counting. In periodic, snap-shot mode, (TnSNAPS bit in the GPTMTnMR register is set),
the actual free-running value of the timer at the time-out event is loaded into the GPTMTAR register.
In this manner, software can determine the time elapsed from the interrupt assertion to the ISR
entry.
In addition to reloading the count value, the timer generates interrupts and triggers when it reaches
the time-out event. The GPTM sets the TnTORIS bit in the GPTMRIS register, and holds it until it
is cleared by writing the GPTMICR register. If the time-out interrupt is enabled in GPTIMR, the
GPTM also sets the TnTOMIS bit in GPTMISR and generates a controller interrupt. By setting the
TnMIE bit in the GPTMTnMR register, an interrupt can also be generated when the timer value
equals the value loaded into the GPTM Timer n Match (GPTMTnMATCH) register. This interrupt
has the same status, masking, and clearing functions as the time-out interrupt. The ADC trigger is
enabled by setting the TnOTE bit in the GPTMCTL register. The μDMA trigger is enabled by
configuring and enabling the appropriate μDMA channel. See “Channel Configuration” on page 240.
If software updates the GPTMTnILR register while the counter is counting down, the counter loads
the new value on the next clock cycle and continues counting down from the new value. If software
updates the GPTM Timer n Value (GPTMTnV) register while the counter is counting up or down,
the counter loads the new value on the next clock cycle and continues counting from the new value.
If the TnSTALL bit in the GPTMCTL register is set, the timer freezes counting while the processor
is halted by the debugger. The timer resumes counting when the processor resumes execution.
The following example shows a variety of configurations for a 16-bit free-running timer while using
the prescaler. All values assume an 80-MHz clock with Tc=12.5 ns (clock period).
Table 11-4. 16-Bit Timer With Prescaler Configurations
Prescale
#Clock (Tc)^a
00000000
1
00000001
2
00000010
3
------------
--
11111101
254
11111110
255
11111111
256
a. Tc is the clock period.
Max Time
0.8192
1.6384
2.4576
--
208.0768
208.896
209.7152
Units
mS
mS
mS
--
mS
mS
mS
11.3.3.2
Input Edge-Count Mode
Note: For rising-edge detection, the input signal must be High for at least two system clock periods
following the rising edge. Similarly, for falling-edge detection, the input signal must be Low
430
June 29, 2010
Texas Instruments-Advance Information