82371AB Datasheet, PDF (98/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
Bit Setting
Cycle Time Bit Settings
Table 13. Ultra DMA/33 Timing Mode Settings
Mode 0
(120 ns Strobe Period)
Mode 1
(90 ns Strobe Period)
00
01
Mode 2
(60 ns Strobe Period)
10
Table 14. DMA/PIO Timing Values (Based on PIIX4 Cable Mode and System Speed)
PIIX4 Drive
Mode
IORDY
Recovery
Sample Point Time (RCT)
(ISP)
IDETIM[15:8] IDETIM[15:8]
Drive 0
Drive 0
(Master)
(Master)
If Slave
Attached
If no Slave
attached or
Slave is
Mode 0¹
SIDETIM
Pri[3:0]
Sec[7:4]
Drive 1
(Slave)
Resultant
Cycle Time
Base operating
frequency and
cycle time
PIO0/
5 clocks
4 clocks
C0h
80h
0
30 MHz: 900 ns
Compatible
(default)
(default)
33 MHz: 900 ns
PIO2/SW2
4 clocks
4 clocks
D0h
90h
4
30 MHz: 256 ns
33 MHz: 240 ns
PIO3/MW1
3 clocks
3 clocks
E1h
A1h
9
30 MHz: 198 ns
33 MHz: 180 ns
PIO4/MW2
3 clocks
1 clock
E3h
A3h
B
30 MHz: 132 ns
33 MHz: 120 ns
NOTES:
1. This table assumes that if the attached slave drive is Mode 0 or is not present, the SITRE bit is set to 0.
2. The table assumes that 25 MHz is not supported as a target PCI system speed. If the DMA Timing Enable
Only (DTE) bit has been enabled for that drive, this resultant cycle time applies to data transfers performed
with DMA only.
98
PRELIMINARY
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)