82371AB Datasheet, PDF (120/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
7.1.8. INTLN—INTERRUPT LINE REGISTER (FUNCTION 3)
Address Offset:
Default Value:
Attribute:
3Ch
00h
Read/Write
Software programs this register with interrupt information concerning the Power Management module.
Bit
Description
7:0 Interrupt Line. The value in this register has no affect on PIIX4 hardware operations.
7.1.9. INTPN—INTERRUPT PIN (FUNCTION 3)
Address Offset:
Default Value:
Attribute:
3Dh
01h
Read only
This register indicates that PCI interrupt pin PIRQA# is used for the Power Management module.
Bit
Description
7:3 Reserved.
2:0 Serial Bus Module Interrupt Routing. This field is hardwired to 01h to indicate that PCI interrupt
pin PIRQA# is used.
7.1.10. PMBA—POWER MANAGEMENT BASE ADDRESS (FUNCTION 3)
Address Offset:
Default Value:
Attribute:
40−43h
00000001h
Read/Write
This register contains the base address of the Power Management I/O Registers.
Bit
Description
31:16 Reserved. Hardwired to 0s. Must be written as 0s.
15:6 Index Register Base Address. Bits [15:6] correspond to I/O address signals AD [15:6],
respectively.
5:1 Reserved. Read as 0.
0 Resource Type Indicator (RTE)—RO. This bit is hardwired to 1 indicating that the base address
field in this register maps to I/O space.
120
PRELIMINARY
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)