82371AB Datasheet, PDF (42/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
3.0. REGISTER ADDRESS SPACE
PIIX4 internal registers are organized into four functions—ISA Bridge with integrated AT compatibility logic, IDE
Controller, USB Host Controller, and Enhanced Power Management. Each function has its registers divided into
one set of PCI Configuration Registers and one or more register sets located in system IO space.
Some of the PIIX4 registers contain reserved bits. Software must deal correctly with fields that are reserved. On
reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any
particular value. On writes, software must ensure that the values of reserved bit positions are preserved. That is,
the values of reserved bit positions must first be read, merged with the new values for other bit positions and
then written back.
In addition to reserved bits within a register, the PIIX4 contains address locations in the PCI configuration space
that are marked “Reserved.” The PIIX4 responds to accesses to these address locations by completing the Host
cycle. Software should not write to reserved PIIX4 configuration locations in the device-specific region (above
address offset 3Fh).
During a hard reset, the PIIX4 sets its internal registers to predetermined default states. The default values are
indicated in the individual register descriptions.
The following notation is used to describe register access attributes:
RO
WO
R/W
R/WC
Read Only. If a register is read only, writes have no effect.
Write Only. If a register is write only, reads have no effect.
Read/Write. A register with this attribute can be read and written. Note that individual bits in some
read/write registers may be read only.
Read/Write Clear. A register bit with this attribute can be read and written. However, a write of a 1
clears (sets to 0) the corresponding bit and a write of a 0 has no effect.
3.1. PCI/ISA Bridge Configuration
The PIIX4 PCI function 0 contains a PCI to ISA bridge along with standard AT compatible logic including DMA
controller, Interrupt controller, and counter/timers. This function also contains support for a real time clock and
PCI based DMA. The register set associated with PCI to ISA Bridge and associated logic is shown below with
actual register descriptions given in the “PCI to ISA/EIO Bridge Register Description” section.
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