82371AB Datasheet, PDF (230/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
Table 35. Power State Decode
Power State
On
RSMRST# SUS_STAT1# SUS_STAT2#
1
x¹
1
SUSA#
1
SUSB#
1
SUSC#
1
POS
1
0
0
0
1
1
STR
1
0
0
0
0
1
STD/SOFF
1
0
0
0
0
0
Mechanical Off
0
0
0
0
0
0
NOTES:
1. SUS_STAT1# is also used when the system is running. It indicates to the Host-to-PCI bridge when to switch
between the normal and suspend refresh mode for DRAM Stop Clock support. In the Stop Clock condition,
HCLK is stopped and the Host-to-PCI bridge must run DRAM refresh off the SUSCLK input.
11.4.2. SYSTEM RESUME
PIIX4 can be resumed from either a Suspend or Soft Off state. Depending on the system’s suspend state,
different features can be enabled to resume the system. There are two classes of resume events, those whose
logic resides in the PIIX4 main power well and those whose logic resides in the PIIX4 Suspend well. Those in the
Suspend well can resume the system from any Suspend or Soft Off state. Those in the main power well can only
resume the system from a Powered On Suspend state. Table 36 lists the suspend states that can be enabled for
a particular resume event.
Upon detection of an enabled resume event, PIIX4 will set appropriate status signals and automatically transition
its suspend control signals bringing the system into a “full on” condition. The sequencing is shown in the “System
Suspend And Resume Control Signaling” section.
Table 36. Resume Events Supported In Different Power States
Suspend States
Resume Event
POS
STR
STD/SOff
RTC Alarm (IRQ8)*
x
x
x
SMBus Resume Event (Slave Port Match)
x
x
x
Serial A Ring (RI)
x
x
x
Power Button (PWRBTN#)
x
x
x
EXTSMI (EXTSMI#)
x
x
x
LID (LID)
x
x
x
GPI1
x
x
x
GSTBY Timer Expiration
x
x
x
Interrupt (IRQ[1,3:15])
x
USB
x
MOff
The various resume events and their programming model are shown here.
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