82371AB Datasheet, PDF (116/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
Bit
Description
5:4 Line Status—RO. These bits reflect the D+ (bit 4) and D– (bit 5) signals lines’ logical levels. These
bits are used for fault detect and recovery as well as for USB diagnostics. This field is updated at
EOF2 time (See Chapter 11 of the USB Specification).
3 Port Enable/Disable Change—R/WC. 1=Port enabled/disabled status has changed. 0=No change.
For the root hub, this bit gets set only when a port is disabled due to disconnect on that port or due to
the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification).
Software clears this bit by writing a 1 to it.
2 Port Enabled/Disabled—R/W. 1=Enable. 0=Disable. Ports can be enabled by host software only.
Ports can be disabled by either a fault condition (disconnect event, overcurrent condition, or other
fault condition) or by host software. Note that the bit status does not change until the port state
actually changes and that there may be a delay in disabling or enabling a port if there is a transaction
currently in progress on the USB.
1 Connect Status Change—R/WC. 1=Change in Current Connect Status. 0=No change.
Indicates a change has occurred in the port’s Current Connect Status (see bit 0). The hub device
sets this bit for any changes to the port device connect status, even if system software has not
cleared a connect status change. If, for example, the insertion status changes twice before system
software has cleared the changed condition, hub hardware will be “setting” an already-set bit (i.e.,
the bit will remain set). However, the hub transfers the change bit only once when the Host
Controller requests a data transfer to the Status Change endpoint. System software is responsible
for determining state change history in such a case. Software sets this bit to 0 by writing a 1 to it.
0 Current Connect Status—RO. 1=Device is present on port. 0=No device is present. This value
reflects the current state of the port, and may not correspond directly to the event that caused the
Connect Status Change bit (Bit 1) to be set.
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