82371AB Datasheet, PDF (253/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
Table 48. STR to On Timings
Sym
Parameter
Min Max Unit Notes
t86 Resume Event to SUS[A:B]# Inactive
1
RTC
1
t87 SUS[A:B]# Inactive to Core Well Power Applied
0
ns
t88 Core Well Power Applied to PCI_STP# and CPU_STP# Float
0
ns
t89 Core Well Power Applied to PCI_RST# Active
0
ns
t90 Core Well Power Applied to CPURST Active
0
ns
t91 Core Well Power Applied to SLP# Inactive
0
ns
t92 Core Well Power Applied to STPCLK# Inactive
0
ns
t93 PCI_STP# and CPU_STP# Float to Clocks Running
2
t94 Core Well Power Applied to PWROK Active
1
ms
t95 PWROK Active to CPU_STP# and PCI_STP# Active
0
ns
t96 PCI_STP# and CPU_STP# Active to Clocks Stopped
2 PCICLK 3
t97 PWROK Active to CPU_STP# and PCI_STP# Inactive
1
RTC
1
t98 SUS[A:B]# Inactive to CPU_STP# and PCI_STP# Inactive
16
ms
t99 CPU_STP# and PCI_STP# Inactive to Clocks Running
2 PCICLK 3
t100 CPU_STP# and PCI_STP# Inactive to SUS_STAT[1:2]# Inactive 1
ms
t101 SUS_STAT[1:2]# Inactive to CPU_STP# and PCI_STP# allowed 2
to change
RTC
1
t101a SUS_STAT[1:2]# Inactive to PCI_RST# Inactive
1
RTC
1
t102 PCI_RST# Inactive to CPURST Inactive
1
RTC
1
NOTES:
1. These signals are controlled off the internal RTC clock. 1 RTC is approximately 32 µs.
2. There are no specific requirements for these timings related to PIIX4. The system manufacturer should
make sure that the clocks on power up meet any other system specifications. As a minimum, the clocks
must be available and stable after time t99.
3. See Figure 18 and Figure 19 for exact PCICLK requirements for use with PC/PCI DMA and Serial IRQs.
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