82371AB Datasheet, PDF (45/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
Address
0070h²
0070h²
0071h²
0072h
0073h
0080h^5,6
0081h⁵
0082h⁵
0083h⁵
0084h^5,6
0085h^5,6
0086h^5,6
0087h⁵
0088h^5,6
0089h⁵
008Ah⁵
008Bh⁵
008Ch^5,6
008Dh^5,6
008Eh^5,6
008Fh⁵
0092h
00A0h
00A1h
Aliased
Addresses
0072h,³ 0074h,
0076h
0072h,³ 0074h,
0076h
0073h,⁴
0075h, 0077h
0090h
0091h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A4h, 00A8h,
00ACh, 00B0h,
00B4h, 00B8h,
00BCh
00A5h, 00A9h,
00Adh, 00B1h,
00B5h, 00B9h,
00BDh
Table 5. ISA-Compatible Registers
Type
Register Name
WO NMI Enable
WO RTC Index
R/W RTC Data
R/W RTC Extended Index
R/W RTC Extended Data
R/W DMA1 Page (Reserved)
R/W DMA1 CH2 Low Page (CH2)
R/W DMA1 CH3 Low Page (CH3)
R/W DMA1 CH1 Low Page (CH1)
R/W DMA1 Page (Reserved)
R/W DMA1 Page (Reserved)
R/W DMA1 Page (Reserved)
R/W DMA1 CH0 Low Page (CH0)
R/W DMA Page (Reserved)
R/W DMA2 CH2 Low Page (CH6)
R/W DMA2 CH3 Low Page (CH7)
R/W DMA2 CH1 Low Page (CH5)
R/W DMA2 Page (Reserved)
R/W DMA2 Page (Reserved)
R/W DMA2 Page (Reserved)
R/W DMA2 Low Page Refresh
R/W Port 92
R/W Initialization Command Word 1 (INT-2)
Operational Command Word 2 (INT-2)
Operational Command Word 3 (INT-2)
R/W Initialization Command Word 2 (INT-2)
Initialization Command Word 3 (INT-2)
Initialization Command Word 4 (INT-2)
Operational Command Word 1 (INT-2)
PRELIMINARY
Access
PCI/ISA
PCI/ISA
PCI/ISA
PCI/ISA
PCI/ISA
PCI/ISA
PCI/ISA
PCI/ISA
PCI/ISA
PCI/ISA
PCI/ISA
PCI/ISA
PCI/ISA
PCI/ISA
PCI/ISA
PCI/ISA
PCI/ISA
PCI/ISA
PCI/ISA
PCI/ISA
PCI/ISA
PCI/ISA
PCI/ISA
PCI/ISA
45
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)