82371AB Datasheet, PDF (51/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
Table 10. PCI CONFIGURATION REGISTERS (FUNCTION 3)
Address Offset Mnemonic
Register Name
7C–7Fh
80h
DEVRESJ
PMREGMISC
Device Resource J
Miscellaneous Power Management
81–8Fh
90–93h
—
SMBBA
Reserved
SMBus Base Address
94–D1h
D2h
—
SMBHSTCFG
Reserved
SMBus Host Configuration
D3h
SMBREV
SMBus Revision ID
D4h
SMBSLVC
SMBus Slave Command
D5h
SMBSHDW1
SMBus Slave Shadow Port 1
D6h
D7–FFh
SMBSHDW2
—
SMBus Slave Shadow Port 2
Reserved
3.4.1. IO SPACE REGISTERS
Table 11. Power Management I/O Registers
Offset From Mnemonic
Base Address
Register Name
00–01h
02–03h
PMSTS
PMEN
Power Management Status
Power Management Resume Enable
04–05h
06–07h
PMCNTRL
—
Power Management Control
Reserved
08h
09–0Bh
PMTMR
—
Power Management Timer
Reserved
0C–0Dh
0E–0Fh
GPSTS
GPEN
General Purpose Status
General Purpose Enable
10–13H
PCNTRL
Processor Control
14h
PLVL2
Processor Level 2
15h
PLVL3
Processor Level 3
16–17h
18–19h
—
GLBSTS
Reserved
Global Status
1A–1Bh
1Ch–1Fh
—
DEVSTS
Reserved
Device Status
20–21h
22–27h
GLBEN
—
Global Enable
Reserved
28–2Bh
2C–2Fh
GLBCTL
DEVCTL
Global Control
Device Control
PRELIMINARY
Access
R/W
R/W
—
R/W
—
R/W
RO
R/W
R/W
R/W
—
Access
R/W
R/W
R/W
—
R/W
—
R/W
R/W
R/W
R/W
R/W
—
R/W
—
R/W
R/W
—
R/W
R/W
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4/9/97 2:23 PM PIIX4aDS
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