82371AB Datasheet, PDF (74/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
4.2.1.12.
DCLM—DMA Clear Mask Register (IO)
I/O Address:
Default Value:
Attribute:
Channel 0–3—00Eh; Channel 4–7—0DCh
All bits undefined
Write Only
This command clears the mask bits of all four channels, enabling them to accept DMA requests.
Bit
Description
7:0 Clear Mask Register. No specific pattern. Command enabled with a write to the I/O port address.
4.2.2. INTERRUPT CONTROLLER REGISTERS
PIIX4 contains an ISA-Compatible interrupt controller that incorporates the functionality of two 82C59 interrupt
controllers. The interrupt registers control the operation of the interrupt controller.
4.2.2.1.
ICW1—Initialization Command Word 1 Register (IO)
I/O Address:
Default Value:
Attribute:
INT CNTRL-1—020h; INT CNTRL-2—0A0h
All bits undefined
Write Only
A write to Initialization Command Word 1 starts the interrupt controller initialization sequence. Addresses 020h
and 0A0h are referred to as the base addresses of CNTRL-1 and CNTRL-2, respectively. An I/O write to the
CNTRL-1 or CNTRL-2 base address with bit 4 equal to 1 is interpreted as ICW1. For PIIX4-based ISA systems,
three I/O writes to “base address + 1” must follow the ICW1. The first write to “base address + 1” performs
ICW2, the second write performs ICW3, and the third write performs ICW4.
ICW1 starts the initialization sequence during which the following automatically occur:
1. The Interrupt Mask register is cleared.
2. IRQ7 input is assigned priority 7.
3. The slave mode address is set to 7.
4. Special Mask Mode is cleared and Status Read is set to IRR.
5. If IC4 was set to 0, then all functions selected by ICW4 are set to 0. However, ICW4 must be programmed in
the PIIX4 implementation of this interrupt controller, and IC4 must be set to a 1.
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